rus
Issue #4/2015
V.Verner, E.Kuznetsov, A.Saurov
Fiftieth anniversary of Moore’s Law: scaling of IC elements
Fiftieth anniversary of Moore’s Law: scaling of IC elements
The first part of the series of publications devoted to the 50th anniversary of Moore’s Law discusses the correlation between the scaling of IC elements and Moore’s Law
In the early days of integrated electronics based on silicon, G.Moore, who headed Fairchild Semiconductor at the time, formulated the further development trend of electronics. It was necessary to prove that integrated circuits were more profitable than solutions on discrete elements. Therefore, research was conducted around the correlation between the price of ICs and conditions of their manufacture, i.e. technology. According to observations, the least price depended on the technological level, which was changing over time (fig.1).
The technological level was determined by the number of transistors in a circuit, which later was known as "the degree of integration" (fig.2).
Meaning and Foundation of Moore’s Law
In the beginning, Moore concluded that the number of transistors in the condition of cost minimization doubled each year. The subsequent analysis of IC development, conducted in 1975, convinced Moore that the degree of integration doubled every two years. G.Moore’s merit was that he formulated the target pace in development of IC design and manufacture. Setting the IC development pace was described in [2] as the main achievement of Moore’s Law, and it was compared to such epochal phenomenon as Internet.
In [2], Moore’s Law was called a "battle drum" that set up the pace of development. Either you keep up with this pace or you lose. A less aggressive title of Moore’s Law, though having the same meaning, was "the Metronome of the Silicon Valley" [3].
Moore’s Law determined the development pace of microelectronics exponentially, which was expressed in the twofold change in the price of ICs and in the degree of integration, occurring every two years (fig.3) [4, 5].
However, it turned out that the two-year pace of change had limitations. Further analysis showed that it slowed down (fig.4). Despite this, it can be certainly stated that there is still a possibility to formulate the change pattern in the microelectronics development rate, so Moore’s Law is working.
The differences in the evaluation of Moore’s Law are related to its ambivalence. In the beginning, it was formulated as an economic law of exponential development of the new IC market, but it was based on the exponential growth of technology. The requirements for introduction of changes in the technology at a certain pace became the main perceived signs of Moore’s Law. The economic component, while remaining important, was pushed in the evaluation of the Law to the background.
The effect of Moore’s Law is supposed to result in a reduction of price. But the price of what? The price of the main functional element, i.e. the transistor, or of a more dimensional function? Let us start with the first one.
An increase in the degree of integration, besides the reduction of the cost, is accompanied by improved performance of ICs. Thus, the performance of microprocessors at this pace of integration doubles every 18 months, which is due to the increase in the number of transistors and the reduction of delays in IC signals. Because of this Law, similar improvements can be formulated too for other characteristics of ICs, such as power consumption, cost, performance etc. Thus, Moore’s Law frequently implies all the impacts of its formulation. In this form, Moore’s Law made a transition from the sphere of economics to the sphere of technical forecasts. In this form, it gained fame and became a stimulus for microelectronics development.
In practice, Moore’s Law involves planning and organizing scientific and technological activity, determining its areas and setting problems in a way that helps to continue the certain trends in the development of microelectronics and, in a broader sense, of all scientific and technical progress. Thus, Moore’s Law set up the rapid development of microelectronics, which resulted in the formation of a new technological structure, i.e. an informational society, and was essentially at the foundation of economic progress over the past 50 years. This development has had an undeniable impact on all sectors of production and changed the social and daily life. In microelectronics, Moore’s Law have resulted in the acceleration of scientific and technological revolution and the emergence of new interdisciplinary areas such as nanotechnology, artificial intelligence and cognitive technologies.
Increasing the degree of integration in IC is naturally associated with the reduction of the area of the elements, e.g., transistors. This reduction (scaling) is proportionate to the scaling factor S. It is noteworthy that if the first decade of microelectronics saw various circuit designs and, hence, all kinds of technologies (bipolar, MOSFET transistor based), but since 1970s, the champion has been CMOS basis of complementary (p- and n- channel) MOSFET transistors. Therefore, Moore’s Law implies the scaling of CMOS technologies, and, above all, its MOSFET transistor element.
Dennard’s study of MOSFET field-effect transistor scaling [6, 7] showed that if the field strength does not change, the voltage and delay time reduce by S times. Consequently, the speed increases and the power consumption decreases. Thus, the scaling affects the development of microelectronics via the change in the degree of integration, the IC price and the improvement of the IC performance. Historically, IC scaling had several stages described by their definitions in the ITRS publications. These definitions slightly adapted are given below.
Geometrical scaling
Geometrical scaling means continuous reduction of physical horizontal and vertical dimensions of the functional logic and memory areas due to a higher density of elements and improvement of functional characteristics (speed, capacity and reliability) required for applications of the end customer.
Parameters are scaled after selecting one of them as a constant. The constant field strength or constant voltage was usually taken as a constant factor for scaling [8] (Table 1). Three variants of frequency consideration and a possibility of multi-core structure consideration were studied in the latter case.
It seemed that the scaling resolved miniaturization problems by gradual transition to smaller dimensions of the structural elements of a MOSFET transistor. Indeed, before the design standards of 90 nanometers (2004), large-scale geometrical miniaturization had occurred with a constant electric field, when all the dimensions of a transistor and the voltage changed with the same ratio as the minimum lithographic size. This period was called the Golden Era of miniaturization, because reducing the size of a transistor was a relatively simple task, with small changes in its structure made during the transition from one technological level to another. However, below 90 nanometers, further simple geometrical scaling resulted in deterioration of the transistor characteristics.
Equivalent Scaling
When the thickness of gate oxide decreases below 1.6 nm, the current of direct quantum-mechanical tunneling increases dramatically and the gate dielectric insulator conventionally made of silicon dioxide loses its insulating properties. The solution was found in the use of dielectrics with a high-k of dielectrics.
From the perspective of transistor controllability, i.e. the possibility to control the current in the channel with gate power, it is necessary to have the specific capacitance of gate dielectric Cox increased when scaling miniaturization. In geometrical scaling, this increase was ensured by reducing the thickness of the gate dielectric. However, rather than reducing the thickness, it is possible to increase the dielectric permeability of the gate using another material, which would provide the required value of the Cox, thereby avoiding the increase in the vertical electric field and preventing gate leakage. The used dielectric is characterized by a value "Equivalent to silicon oxide thickness" (EOT). This approach was used even with the design standards of 180 nm. As an alternative dielectric before the standard of 65 nm there was silicon oxynitride with the share of nitride increased in scaling (and thus increasing the dielectric permeability up to 8–9). Starting with the design standards 45 nm, the gate dielectrics were made of such materials as HfO2 and ZrO2. The replacement of SiO2 with other dielectrics was the first example of "equivalent scaling".
Gate doped polysilicon used during the "Golden Era" of scaling is degenerate semiconductor with a maximum concentration of about 1020 cm-3, therefore, it creates a carrier depletion layer at the boundary with the gate dielectric at working voltages and the corresponding depletion capacitance. Because this capacitance was not scalable, it was necessary to make transition to new metallic materials for gate. The new material had to have a specific output needed for setting the threshold voltage of the transistor. This transition was made at the time of design standards of 45 nm (2007) together with the simultaneous replacement of silicon oxynitride with new dielectrics.
The newly created "equivalent" gate node in the English literature was designated as HKMG (High-K/Metal Gate). For example, in the IMEC study, valves from a TiN (for an n-channel transistor) and TaN (a p-channel) were used, and the gate was made from HfO2, which provided EOT less than 1 nm.
In miniaturization, the "equivalent" gate node was used to keep the vertical field constant in the transistor, despite a systematic slowdown in the reduction of the power supply voltage. Therefore, starting with design standards of 90 nanometers, further scaling of the transistor was carried out with constant vertical and increasing horizontal components of the electric field. This scenario of scaling was sharply marked by spurious "short-channel effects", which is essentially an increase in the influence of voltages at the drain and source electrodes of the transistor on the current flowing in the channel that leads to degradation of the functional characteristics of the transistor. Special methods of "channel engineering" were developed to suppress these spurious effects, which was the creation of a specific doping profile in the channel and drains/sources by high-energy ion implantation at different angles of the dopant atoms.
Another effect, which severely limited the performance of the transistor, was the resistance of drains/sources, which did not allow geometrical scaling either. The problem was resolved by "equivalent scaling", i.e. gradual transition to new materials in the shunting of this resistance, from TiSi2 (design standards of 350–250 nm) to CoSi2 (90 nm) and then to NiSi (65–45 nm), and the use of "elevated" epitaxial drains/sources and SiGe as an intermediate layer between silicide and silicon.
Upon reaching the design standards of 28–22 nm, the conventional structure of a MOS transistor was exhausted. A strong increase in the tunneling current of the drain/source-substrate resulted in a significant deterioration of performance. The industry made transition to the so-called "fully depleted" structures of silicon-on-insulator (FD SOI) transistors and FinFET transistors. Here, the "equivalent" scaling is related to the use of new structures with nanoscale thickness of the working silicon layer (the area under the gate). Fully depleted transistors were named "multi-gate" transistors (MugFET). Conventionally, FD SOI may be viewed as a one-gate transistor, whereas FinFET is a two-gate transistor. It is expected that with further scaling, the effective multi-gate feature of transistor structures and the "equivalent" component in scaling elements will only grow.
Thus, the equivalent scaling means improved performance of 2D and 3D structures, not due to changes in the typical geometrical parameters, but due to the use of new materials, new processes and new integrated structures. Equivalent scaling can be used either without geometrical scaling or with it, complementing each other. fig.5 shows the ratio of the contributions of geometric and equivalent scaling to the improvement of the IC performance in 1999-2011
Functional scaling
A system implemented to perform specific functions using a particular technology is called functional scaling if it can be implemented using alternative technologies so that its functions are identical to the original functions of the system, while at least one of its performance parameters improves and others deteriorate. In practice, functional scaling involves designing an IC for which subsequent manufacturing is possible using different design standards.
Equivalent scaling based on the design
Scaling of IC elements poses challenges that are directly related to the design of ICs as a system. Therefore, it is necessary to develop new design methods that allow scaling with better IC performance parameters, including power consumption and cost, in line with Moore’s Law. This approach is called "design-based equivalent scaling". It includes geometrical and equivalent scaling of IC elements and allows achieving improved performance, packing density and other indicators, using non-geometrical methods. The correlation between types of scaling is shown in fig.6.
Various methods of equivalent scaling (both integral elements and design-based scaling) can be applied for different types of ICs. This resulted in improved performance according to Moore’s Law becoming a characteristic for a specific type of ICs. Thus, with further scaling, there is further differentiation and specialization of ICs at the level of design, technological processes and design standards.
Therefore, in a general sense, scaling should be understood as methods of improving the working and functional characteristics of a device, from a transistor to the whole system.
Among the reviewed methods of scaling, the important one is related to reducing the size, i.e. the geometrical scaling. In this case, the scaling factor S provides the magnitude of relative changes in geometrical dimensions.
Absolute values can be obtained if the measurement of the minimum characteristic size f is determined. The determination of the characteristic size is described in the publications of the ITRS on horizontal or vertical cross sections of transistor elements [11]. The most often used value is equal to half of the pitch between the lines of conductors (half-pitch – h-p) of the first layer of metallization for DOSE IC or half step of polysilicon buses for flash memory.
In principle, this determination may be used for logic ICs, including microprocessors (MPs). However, the length of the gate is more often used as f for MPs: physical gate length (GLph) or printed gate length (GL). This difference in the determination of f is caused by the difference in the critical parameters of the memory and MPs. For IC memory, the degree of integration is critical, which can be characterized by the value (h-p). For MP, speed is critical, determined via GLph.
The change of (h-p) occurs at 0.71 per one temporal cycle or 0.5 per two temporal cycles. In 2013 (h-p) was changed in a three year cycle – by 0.5 in 6 years. It is expected that 2017 the two-year cycle will resume.
While, in geometrical scaling, the minimum characteristic size f fully determined the technological level, it loses its value with the increasing role of equivalent scaling. Therefore characteristic scaling measure was introduced, called a "node" (Node Naming – N), which reflects how the conditional minimum element size would change in full geometrical scaling. The f characteristics of different types of ICs via the values of h-p and N are given in Table 2.
Different types of scaling were used at different stages of development of the semiconductor industry, shown in a comparative table (Table 3).
The power consumption of MOS transistor P, which transforms into heat when switching with the frequency f, is derived from dynamic Pdyn and static Pstat powers:
P = Pdyn + Pstat, (1)
Pdyn = CV2dd f, (2)
Pstat = Vd Ioff, (3)
where C is the load capacitance, Ioff is the current in off state (leakage current), Vdd is the supply voltage IC.
The dynamic power consumption can be diminished by reducing the system’s frequency f. The static power of idle blocks can be reduced to zero by disconnecting them from the power supply. These two techniques, which have been widely used in the development of ICs with the design standards below 180 nm, are the first examples of design-based equivalent scaling.
Power consumption is a restricting factor primarily in systems working on accumulators (laptops, tablets, cell phones, etc.). ICs for them are put into a separate low-power class. Circuits, for which the primary factor is the performance and the maximum power consumption is determined by the heat sink, are put into a high performance class.
An example of design-based equivalent scaling is the use of multiprocessor systems. Parallelization of computation with preservation of frequency resulted in increased performance without great increase in power consumption.
Analysis of data on the increasing number of crystal-based transistors in recent years has shown that there was a slowdown (fig.4). Although the progress in the field of lithography ensured, at least until 2013, geometrical scaling in accordance with Moore’s Law, the real growth in transistor density decreased to a ratio of 1.6 since 2007 with each new technological "node". This lag is explained by both economic factors and technical constraints related to reliability, operating conditions and design architecture, as well as the increasing variability of technological processes. This gap between the lithographic phases of "possible" and "feasible" densities of elements raised the question of the validity of Moore’s Law in its classical formulation.
Adoption of new technologies leads to a significant complication of IC design. This is conncted with significant constraints lain on relative positions of layers, as well as multi-mask lithographs, resulting in a large variability of spurious elements. Consequently, there is an increase in the risks for project profitability.
The situation is redeemed by the methods of design-based equivalent scaling (DES). According to an optimistic forecast, for server and desktop systems processors, DES may replace one node of scaling in the period up to 2020. It is suggested that DES may potentially reduce the size of logic circuits up to 63% of the current size over the next six years and compensate for the 1.6-fold increase in transistor density, i.e. it "saves" Moore’s Law for the near future.
Prospects
Currently, dimensional and functional scaling of CMOS technology is the basis for development and implementation in various applications of information processing technologies – data ingestion, transformation, storage, processing and transmission. Many of these applications have become feasible thanks to the increased performance and complexity of the systems that have been provided by IC scalability. Since geometrical and equivalent CMOS scaling is approaching its fundamental limitation, we need to search for alternative devices and alternative microarchitectures for processing information that would expanded the functionality of the system. This would support scaling while reducing the cost and increasing functionality of the information processing system. There are two possible approaches:
1) expansion of the CMOS platform functionality by integrating of CMOS technology with new technologies of different types;
2) developing a brand new paradigm of information processing.
The division of microelectronics into the individual domains was proposed by ITRS in 2005, and it became widely accepted (fig.7 and 8). The ratio between the aforementioned approaches is schematically shown in fig.9.
The development of a CMOS platform due to different types of scaling is called "More Moore". The expansion of the integrated system is called "More than Moore". New devices for processing information and new architectural approaches were called "Beyond CMOS" technologies. Heterogeneous integration of "beyond CMOS" approaches, as well as "More than Moore" approach, with the emerging "More Moore" platform shape the "CMOS extension". This means that over time the role of technological "bottom-up" paradigm in the production of integrated systems will increase. This general concept of heterogeneous integration provides the possibility of further scaling of information processing systems and provides a transition from the CMOS platform to new nanoelectronics areas.
In general, the processing information system includes several hierarchical and interactive levels. For example, in the design of ICs, these levels may be traced top-down – the architecture is built on defining the purpose of the system and its functions, and then sequentially come: microarchitecture, individual blocks (circuits), elements (transistors and wires), a required technological process (which involves the use of certain materials), which form individual elements and the system as a whole. Each level of the hierarchy has its own technology. However, one can also build bottom-up hierarchy by first determining the lowest physical level, i.e. the variable of the informational state, and ending in a system architecture (fig.10).
In this representation, the processing information system has a device level, and the fundamental unit of information is represented by a variable of state, for example, as it is currently done, by the charge (voltage) at the node of the CMOS circuit, or, as it was in the past, by the location of the bone in the abacus. The device in this case is used to represent a physical value and ensures the control of transitions of the informational variable between two or more allowed conditions. It is a physical structure made of different materials with special properties through the sequence of technological operations. Thus, it is possible to identify the most important hierarchical level, which is– the level of materials science and technology. The level of data representation in this hierarchy describes how the variable of state is encoded by a group of devices for processing data. The two best-known examples of data representation are digital and analog signals. The higher level of architecture can be divided into several subclasses. The subclass nano-architecture or functional primitives is used to build another subclass of a computational model of an information processing model, for example, devices for logical or arithmetic transformations, memory, cellular automata chains etc.
In fig.10, the yellow rectangles in a red box highlights the elements corresponding to the CMOS technological platform. It is characterized by the binary data representation based on a variable of state, i.e. electric charge, which serves as the basis for construction of Von Neumann’s computer architecture. The elements drawn in white boxes in this fig. are grouped into five categories and they represent some of the most promising innovative technologies that can become the basis of a new scaling paradigm for processing information systems. ■
The technological level was determined by the number of transistors in a circuit, which later was known as "the degree of integration" (fig.2).
Meaning and Foundation of Moore’s Law
In the beginning, Moore concluded that the number of transistors in the condition of cost minimization doubled each year. The subsequent analysis of IC development, conducted in 1975, convinced Moore that the degree of integration doubled every two years. G.Moore’s merit was that he formulated the target pace in development of IC design and manufacture. Setting the IC development pace was described in [2] as the main achievement of Moore’s Law, and it was compared to such epochal phenomenon as Internet.
In [2], Moore’s Law was called a "battle drum" that set up the pace of development. Either you keep up with this pace or you lose. A less aggressive title of Moore’s Law, though having the same meaning, was "the Metronome of the Silicon Valley" [3].
Moore’s Law determined the development pace of microelectronics exponentially, which was expressed in the twofold change in the price of ICs and in the degree of integration, occurring every two years (fig.3) [4, 5].
However, it turned out that the two-year pace of change had limitations. Further analysis showed that it slowed down (fig.4). Despite this, it can be certainly stated that there is still a possibility to formulate the change pattern in the microelectronics development rate, so Moore’s Law is working.
The differences in the evaluation of Moore’s Law are related to its ambivalence. In the beginning, it was formulated as an economic law of exponential development of the new IC market, but it was based on the exponential growth of technology. The requirements for introduction of changes in the technology at a certain pace became the main perceived signs of Moore’s Law. The economic component, while remaining important, was pushed in the evaluation of the Law to the background.
The effect of Moore’s Law is supposed to result in a reduction of price. But the price of what? The price of the main functional element, i.e. the transistor, or of a more dimensional function? Let us start with the first one.
An increase in the degree of integration, besides the reduction of the cost, is accompanied by improved performance of ICs. Thus, the performance of microprocessors at this pace of integration doubles every 18 months, which is due to the increase in the number of transistors and the reduction of delays in IC signals. Because of this Law, similar improvements can be formulated too for other characteristics of ICs, such as power consumption, cost, performance etc. Thus, Moore’s Law frequently implies all the impacts of its formulation. In this form, Moore’s Law made a transition from the sphere of economics to the sphere of technical forecasts. In this form, it gained fame and became a stimulus for microelectronics development.
In practice, Moore’s Law involves planning and organizing scientific and technological activity, determining its areas and setting problems in a way that helps to continue the certain trends in the development of microelectronics and, in a broader sense, of all scientific and technical progress. Thus, Moore’s Law set up the rapid development of microelectronics, which resulted in the formation of a new technological structure, i.e. an informational society, and was essentially at the foundation of economic progress over the past 50 years. This development has had an undeniable impact on all sectors of production and changed the social and daily life. In microelectronics, Moore’s Law have resulted in the acceleration of scientific and technological revolution and the emergence of new interdisciplinary areas such as nanotechnology, artificial intelligence and cognitive technologies.
Increasing the degree of integration in IC is naturally associated with the reduction of the area of the elements, e.g., transistors. This reduction (scaling) is proportionate to the scaling factor S. It is noteworthy that if the first decade of microelectronics saw various circuit designs and, hence, all kinds of technologies (bipolar, MOSFET transistor based), but since 1970s, the champion has been CMOS basis of complementary (p- and n- channel) MOSFET transistors. Therefore, Moore’s Law implies the scaling of CMOS technologies, and, above all, its MOSFET transistor element.
Dennard’s study of MOSFET field-effect transistor scaling [6, 7] showed that if the field strength does not change, the voltage and delay time reduce by S times. Consequently, the speed increases and the power consumption decreases. Thus, the scaling affects the development of microelectronics via the change in the degree of integration, the IC price and the improvement of the IC performance. Historically, IC scaling had several stages described by their definitions in the ITRS publications. These definitions slightly adapted are given below.
Geometrical scaling
Geometrical scaling means continuous reduction of physical horizontal and vertical dimensions of the functional logic and memory areas due to a higher density of elements and improvement of functional characteristics (speed, capacity and reliability) required for applications of the end customer.
Parameters are scaled after selecting one of them as a constant. The constant field strength or constant voltage was usually taken as a constant factor for scaling [8] (Table 1). Three variants of frequency consideration and a possibility of multi-core structure consideration were studied in the latter case.
It seemed that the scaling resolved miniaturization problems by gradual transition to smaller dimensions of the structural elements of a MOSFET transistor. Indeed, before the design standards of 90 nanometers (2004), large-scale geometrical miniaturization had occurred with a constant electric field, when all the dimensions of a transistor and the voltage changed with the same ratio as the minimum lithographic size. This period was called the Golden Era of miniaturization, because reducing the size of a transistor was a relatively simple task, with small changes in its structure made during the transition from one technological level to another. However, below 90 nanometers, further simple geometrical scaling resulted in deterioration of the transistor characteristics.
Equivalent Scaling
When the thickness of gate oxide decreases below 1.6 nm, the current of direct quantum-mechanical tunneling increases dramatically and the gate dielectric insulator conventionally made of silicon dioxide loses its insulating properties. The solution was found in the use of dielectrics with a high-k of dielectrics.
From the perspective of transistor controllability, i.e. the possibility to control the current in the channel with gate power, it is necessary to have the specific capacitance of gate dielectric Cox increased when scaling miniaturization. In geometrical scaling, this increase was ensured by reducing the thickness of the gate dielectric. However, rather than reducing the thickness, it is possible to increase the dielectric permeability of the gate using another material, which would provide the required value of the Cox, thereby avoiding the increase in the vertical electric field and preventing gate leakage. The used dielectric is characterized by a value "Equivalent to silicon oxide thickness" (EOT). This approach was used even with the design standards of 180 nm. As an alternative dielectric before the standard of 65 nm there was silicon oxynitride with the share of nitride increased in scaling (and thus increasing the dielectric permeability up to 8–9). Starting with the design standards 45 nm, the gate dielectrics were made of such materials as HfO2 and ZrO2. The replacement of SiO2 with other dielectrics was the first example of "equivalent scaling".
Gate doped polysilicon used during the "Golden Era" of scaling is degenerate semiconductor with a maximum concentration of about 1020 cm-3, therefore, it creates a carrier depletion layer at the boundary with the gate dielectric at working voltages and the corresponding depletion capacitance. Because this capacitance was not scalable, it was necessary to make transition to new metallic materials for gate. The new material had to have a specific output needed for setting the threshold voltage of the transistor. This transition was made at the time of design standards of 45 nm (2007) together with the simultaneous replacement of silicon oxynitride with new dielectrics.
The newly created "equivalent" gate node in the English literature was designated as HKMG (High-K/Metal Gate). For example, in the IMEC study, valves from a TiN (for an n-channel transistor) and TaN (a p-channel) were used, and the gate was made from HfO2, which provided EOT less than 1 nm.
In miniaturization, the "equivalent" gate node was used to keep the vertical field constant in the transistor, despite a systematic slowdown in the reduction of the power supply voltage. Therefore, starting with design standards of 90 nanometers, further scaling of the transistor was carried out with constant vertical and increasing horizontal components of the electric field. This scenario of scaling was sharply marked by spurious "short-channel effects", which is essentially an increase in the influence of voltages at the drain and source electrodes of the transistor on the current flowing in the channel that leads to degradation of the functional characteristics of the transistor. Special methods of "channel engineering" were developed to suppress these spurious effects, which was the creation of a specific doping profile in the channel and drains/sources by high-energy ion implantation at different angles of the dopant atoms.
Another effect, which severely limited the performance of the transistor, was the resistance of drains/sources, which did not allow geometrical scaling either. The problem was resolved by "equivalent scaling", i.e. gradual transition to new materials in the shunting of this resistance, from TiSi2 (design standards of 350–250 nm) to CoSi2 (90 nm) and then to NiSi (65–45 nm), and the use of "elevated" epitaxial drains/sources and SiGe as an intermediate layer between silicide and silicon.
Upon reaching the design standards of 28–22 nm, the conventional structure of a MOS transistor was exhausted. A strong increase in the tunneling current of the drain/source-substrate resulted in a significant deterioration of performance. The industry made transition to the so-called "fully depleted" structures of silicon-on-insulator (FD SOI) transistors and FinFET transistors. Here, the "equivalent" scaling is related to the use of new structures with nanoscale thickness of the working silicon layer (the area under the gate). Fully depleted transistors were named "multi-gate" transistors (MugFET). Conventionally, FD SOI may be viewed as a one-gate transistor, whereas FinFET is a two-gate transistor. It is expected that with further scaling, the effective multi-gate feature of transistor structures and the "equivalent" component in scaling elements will only grow.
Thus, the equivalent scaling means improved performance of 2D and 3D structures, not due to changes in the typical geometrical parameters, but due to the use of new materials, new processes and new integrated structures. Equivalent scaling can be used either without geometrical scaling or with it, complementing each other. fig.5 shows the ratio of the contributions of geometric and equivalent scaling to the improvement of the IC performance in 1999-2011
Functional scaling
A system implemented to perform specific functions using a particular technology is called functional scaling if it can be implemented using alternative technologies so that its functions are identical to the original functions of the system, while at least one of its performance parameters improves and others deteriorate. In practice, functional scaling involves designing an IC for which subsequent manufacturing is possible using different design standards.
Equivalent scaling based on the design
Scaling of IC elements poses challenges that are directly related to the design of ICs as a system. Therefore, it is necessary to develop new design methods that allow scaling with better IC performance parameters, including power consumption and cost, in line with Moore’s Law. This approach is called "design-based equivalent scaling". It includes geometrical and equivalent scaling of IC elements and allows achieving improved performance, packing density and other indicators, using non-geometrical methods. The correlation between types of scaling is shown in fig.6.
Various methods of equivalent scaling (both integral elements and design-based scaling) can be applied for different types of ICs. This resulted in improved performance according to Moore’s Law becoming a characteristic for a specific type of ICs. Thus, with further scaling, there is further differentiation and specialization of ICs at the level of design, technological processes and design standards.
Therefore, in a general sense, scaling should be understood as methods of improving the working and functional characteristics of a device, from a transistor to the whole system.
Among the reviewed methods of scaling, the important one is related to reducing the size, i.e. the geometrical scaling. In this case, the scaling factor S provides the magnitude of relative changes in geometrical dimensions.
Absolute values can be obtained if the measurement of the minimum characteristic size f is determined. The determination of the characteristic size is described in the publications of the ITRS on horizontal or vertical cross sections of transistor elements [11]. The most often used value is equal to half of the pitch between the lines of conductors (half-pitch – h-p) of the first layer of metallization for DOSE IC or half step of polysilicon buses for flash memory.
In principle, this determination may be used for logic ICs, including microprocessors (MPs). However, the length of the gate is more often used as f for MPs: physical gate length (GLph) or printed gate length (GL). This difference in the determination of f is caused by the difference in the critical parameters of the memory and MPs. For IC memory, the degree of integration is critical, which can be characterized by the value (h-p). For MP, speed is critical, determined via GLph.
The change of (h-p) occurs at 0.71 per one temporal cycle or 0.5 per two temporal cycles. In 2013 (h-p) was changed in a three year cycle – by 0.5 in 6 years. It is expected that 2017 the two-year cycle will resume.
While, in geometrical scaling, the minimum characteristic size f fully determined the technological level, it loses its value with the increasing role of equivalent scaling. Therefore characteristic scaling measure was introduced, called a "node" (Node Naming – N), which reflects how the conditional minimum element size would change in full geometrical scaling. The f characteristics of different types of ICs via the values of h-p and N are given in Table 2.
Different types of scaling were used at different stages of development of the semiconductor industry, shown in a comparative table (Table 3).
The power consumption of MOS transistor P, which transforms into heat when switching with the frequency f, is derived from dynamic Pdyn and static Pstat powers:
P = Pdyn + Pstat, (1)
Pdyn = CV2dd f, (2)
Pstat = Vd Ioff, (3)
where C is the load capacitance, Ioff is the current in off state (leakage current), Vdd is the supply voltage IC.
The dynamic power consumption can be diminished by reducing the system’s frequency f. The static power of idle blocks can be reduced to zero by disconnecting them from the power supply. These two techniques, which have been widely used in the development of ICs with the design standards below 180 nm, are the first examples of design-based equivalent scaling.
Power consumption is a restricting factor primarily in systems working on accumulators (laptops, tablets, cell phones, etc.). ICs for them are put into a separate low-power class. Circuits, for which the primary factor is the performance and the maximum power consumption is determined by the heat sink, are put into a high performance class.
An example of design-based equivalent scaling is the use of multiprocessor systems. Parallelization of computation with preservation of frequency resulted in increased performance without great increase in power consumption.
Analysis of data on the increasing number of crystal-based transistors in recent years has shown that there was a slowdown (fig.4). Although the progress in the field of lithography ensured, at least until 2013, geometrical scaling in accordance with Moore’s Law, the real growth in transistor density decreased to a ratio of 1.6 since 2007 with each new technological "node". This lag is explained by both economic factors and technical constraints related to reliability, operating conditions and design architecture, as well as the increasing variability of technological processes. This gap between the lithographic phases of "possible" and "feasible" densities of elements raised the question of the validity of Moore’s Law in its classical formulation.
Adoption of new technologies leads to a significant complication of IC design. This is conncted with significant constraints lain on relative positions of layers, as well as multi-mask lithographs, resulting in a large variability of spurious elements. Consequently, there is an increase in the risks for project profitability.
The situation is redeemed by the methods of design-based equivalent scaling (DES). According to an optimistic forecast, for server and desktop systems processors, DES may replace one node of scaling in the period up to 2020. It is suggested that DES may potentially reduce the size of logic circuits up to 63% of the current size over the next six years and compensate for the 1.6-fold increase in transistor density, i.e. it "saves" Moore’s Law for the near future.
Prospects
Currently, dimensional and functional scaling of CMOS technology is the basis for development and implementation in various applications of information processing technologies – data ingestion, transformation, storage, processing and transmission. Many of these applications have become feasible thanks to the increased performance and complexity of the systems that have been provided by IC scalability. Since geometrical and equivalent CMOS scaling is approaching its fundamental limitation, we need to search for alternative devices and alternative microarchitectures for processing information that would expanded the functionality of the system. This would support scaling while reducing the cost and increasing functionality of the information processing system. There are two possible approaches:
1) expansion of the CMOS platform functionality by integrating of CMOS technology with new technologies of different types;
2) developing a brand new paradigm of information processing.
The division of microelectronics into the individual domains was proposed by ITRS in 2005, and it became widely accepted (fig.7 and 8). The ratio between the aforementioned approaches is schematically shown in fig.9.
The development of a CMOS platform due to different types of scaling is called "More Moore". The expansion of the integrated system is called "More than Moore". New devices for processing information and new architectural approaches were called "Beyond CMOS" technologies. Heterogeneous integration of "beyond CMOS" approaches, as well as "More than Moore" approach, with the emerging "More Moore" platform shape the "CMOS extension". This means that over time the role of technological "bottom-up" paradigm in the production of integrated systems will increase. This general concept of heterogeneous integration provides the possibility of further scaling of information processing systems and provides a transition from the CMOS platform to new nanoelectronics areas.
In general, the processing information system includes several hierarchical and interactive levels. For example, in the design of ICs, these levels may be traced top-down – the architecture is built on defining the purpose of the system and its functions, and then sequentially come: microarchitecture, individual blocks (circuits), elements (transistors and wires), a required technological process (which involves the use of certain materials), which form individual elements and the system as a whole. Each level of the hierarchy has its own technology. However, one can also build bottom-up hierarchy by first determining the lowest physical level, i.e. the variable of the informational state, and ending in a system architecture (fig.10).
In this representation, the processing information system has a device level, and the fundamental unit of information is represented by a variable of state, for example, as it is currently done, by the charge (voltage) at the node of the CMOS circuit, or, as it was in the past, by the location of the bone in the abacus. The device in this case is used to represent a physical value and ensures the control of transitions of the informational variable between two or more allowed conditions. It is a physical structure made of different materials with special properties through the sequence of technological operations. Thus, it is possible to identify the most important hierarchical level, which is– the level of materials science and technology. The level of data representation in this hierarchy describes how the variable of state is encoded by a group of devices for processing data. The two best-known examples of data representation are digital and analog signals. The higher level of architecture can be divided into several subclasses. The subclass nano-architecture or functional primitives is used to build another subclass of a computational model of an information processing model, for example, devices for logical or arithmetic transformations, memory, cellular automata chains etc.
In fig.10, the yellow rectangles in a red box highlights the elements corresponding to the CMOS technological platform. It is characterized by the binary data representation based on a variable of state, i.e. electric charge, which serves as the basis for construction of Von Neumann’s computer architecture. The elements drawn in white boxes in this fig. are grouped into five categories and they represent some of the most promising innovative technologies that can become the basis of a new scaling paradigm for processing information systems. ■
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