rus
Issue #9/2018
Moskovskaya Yulia M., Nikiforov Alexander Yu., Bobrovskiy Dmitry V., Ulanova Anastasiya V., Zhukov A. A.
Estimating the Infl uence of Parameters of the Critical Operations of a Typical CMOS Process on TID Hardness of IC
Estimating the Infl uence of Parameters of the Critical Operations of a Typical CMOS Process on TID Hardness of IC
The influence of 1,5mm CMOS process parameters (mainly gate oxide growth temperature) variations on the total ionizing dose effects is comparatively analyzed in experiment on test structures. It has been experimentally demonstrated that for CMOS processes with gate oxide thickness about 300 Å the TID hardness is obtained in 850–900 °C gate oxide growth temperature range.
Теги: cmos integrated circuits gate oxide growing process temperature manufacturing process tid hardness дозовая стойкость кмоп ис процесс производства процесс формирования подзатворного окисла температура
INTRODUCTION
CMOS ICs are widely used in on-board systems with radiation hardness requirements, that’s why the total ionizing dose (TID) provision within IC design and manufacturing process is a relevant task. Although almost all contemporary publications on TID effects correspond to deep submicron VLSI circuits, according to the authors’ practical experience the majority of ICs used for space applications are manufactured nowadays in the basis of 0.8–5µm design rules and processes. The issues of the impact of the process parameters on CMOS IC TID hardness threshold are widely discussed in literature [1–10]. However, the previously published papers deal with the 20–30-year old processes, and their equivalence with up-to-date processes is not obvious. Therefore the research of the typical space application oriented micron CMOS process parameters influence on their TID threshold seems to be useful. First of all, the obtained results will make it possible to evaluate the equivalence of dominant TID effects and fault mechanisms of up-to-date process to previously investigated processes. Secondly, it gives us useful experience of refining the methodology for CMOS process characterization based on TID hardness levels. And lastly, it will help us to choose parameters rational values for obtaining a compromise between IC (product) functionality and radiation hardness level.
It is well known that TID hardness threshold depends heavily on gate insulator thickness and growth process parameters, in particular on temperature and chemical oxidization environment [1–5]. It is assumed that the oxide growing temperature for TID hardness provision should be within the range of 850–925 °C. Annealing processes conducted under temperatures higher than 950 °C significantly degrade CMOS IC TID hardness [1, 2].
The maximum temperature of the further operations should not exceed the gate oxide growing process temperature [6, 7].
To a lesser extent, TID hardness level is dependent on the atmosphere of oxide growing process [9]. However, it has been experimentally established that wet oxidization in water vapors results in a decrease in total TID-induced charge, which may indicate a decreased number of traps, and thus indicate an increase in TID hardness [10].
So we decided to compare TID hardness of several standard process route versions of micron CMOS IC using test chip samples meant for space systems applications and provided by a typical ASIC designer and manufacturer company.
RADIATIONAL EXPERIMENT DESCRIPTION
A specialized test 5503 series IC gate array manufactured by SMC “Technological Centre” (1.5µm design rules, gate oxide thickness of 325Å) was chosen as the “device under test” (DUT). The test microcircuit included the set of inverter chains and simple logic circuits. IC dies were manufactured utilizing three technological process flow modifications (see Table 1).
The research was performed using 10keV X-ray tester [11] as a radiation source. TID value measurement was performed using BKRI dosimeter with an additional calibration by TID effect equivalence criteria using the linear electron accelerator in bremsstrahlung generation mode (NRNU MEPHI and SPELS Radiation Test Center, Moscow, Russia) [12,13]. The test dose rate was about 10–100rad/s and it has been established that there were no essential dose-rate effects in the used dose rate range [14].
The scheduling of ICs operation modes as well as electrical parameter measurements and functional control and testing during the irradiation were performed with the National Instruments PXI-based hardware and LabVIEW graphical programming environment [15].
TID hardness dependencies of all radiation-sensitive parameters according to the specification such as — static power supply current, low and high output voltages, propagation delay and functional operability — have been measured in every TID point for every IC sample in the experiment.
The previously obtained TID test results of DUT samples from 10 previously manufactured standard process flow lots have been analyzed. It appeared that the static power supply current was the most radiation sensitive parameter.
The typical (average) TID threshold value based on the criteria of power supply current degradation was about 150krad. The TID degradation threshold determined with the functional operability criteria was found to be about 260krad at Ucc = 4.5V and 310krad at Ucc = 5.5V. And the TID threshold of low and high output voltages was 390 krad at Ucc = 4.5V and 5.5V.
Therefore current vs. TID dependencies in standard process route were used as the gold-device reference base for further comparison.
EXPERIMENTAL RESULTS
Figures 1 and 2 present the comparative power supply current vs. dose dependencies for ICs manufactured in standard and modified process routes. It has been established that the power supply current value does not go beyond the values mentioned in technical specifications (400µA) for all process flow modifications up to maximum obtained TID of 3Mrad, whereas for ICs based on the standard process route the TID failure threshold in terms of power supply current was visible at 130 to 170krad.
The results of comparative research into dose sensitivity of different process flow modifications have demonstrated that the best radhard characteristics can be achieved combining 700 °С temperature and oxide growing process in wet atmosphere based on steam generator (Sample 3). The maximum value of power supply current corresponds to oxidization temperature 900 °С and dry oxide (Sample 2). Samples manufactured with oxidization temperature 850 °С and dry oxide, take an intermediate position. It should be noted that the maximum power supply current values were only thrice as large as maximum allowed value for all modified processes.
Thus, decreasing the gate oxide growing temperature from 1000 °С to 900 °С leads to power supply current decrease from hundreds of µA up to units of µA for the TID level of 130krad, leading to CMOS IC hardness threshold increase by an order of magnitude. The further temperature cool-down up to 850 °С leads to negligible reduction in current vs. TID sensitivity: from 3.33µА (900 °С) down to 2.63µА (850 °С) at TID level 1Mrad. The change to the wet oxidization while further oxide growing temperature cool-down up to 700 °С results in TID sensitivity decrease approximately by half, the current being equal to 1.43µА at corresponding dose of 1Mrad.
CONCLUSIONS
It has been experimentally established that for CMOS processes with the gate oxide thickness equal to 325Å the TID hardness is ensured by the gate oxide growth temperature of 850–900 °C, provided that the maximum temperature of the further operations does not exceed the gate oxide growing process temperature. The oxidization in wet environment can reduce the gate oxide growing process temperature up to 700 °C, leading to a decrease in power supply current vs. TID sensitivity, but in this case the reliability of ICs and stability of their electrophysical properties have to be confirmed.
REFERENCES
1. Dawes W. R., Jr., Dervenwick G. F., and Gregory B. L. “Process Technology for Radiation-hardened CMOS Integrated Circuits” // IEEE J Solid-State Circuits. 1976. SC-11, 4.
2. Dressendorfer P. V. “Radiation-Hardening Technology”, in Radiation Effects in MOS Devices and Circuits, Edited by T-P. Ma and Dressendorfer P. V. (Wiley, New York, 1989), pp. 333–400.
3. Shaneyfelt M. R., Schwank J. R., Fleetwood D. M., Winokur P. S., Hughes K. L., Hash G. L. and Connors M. P. “Interface-trap Buildup Rates in Wet and Dry Oxides”, IEEE Trans. Nucl. Sci., Vol. 39, № 6, pp. 2244–2251, 1992.
4. daSilva E. F., Nishioka Y., and Ma T.-P. “Effects of Trichloroethane During Oxide Growth on Radiation-Induced Interface Traps in Metal/SiO /Si Capacitors”, Appl. Phys. Lett., Vol. 51, p. 1262, 1987.
5. Mrstik B. J., Afanas’ev V. V., Stesmans A., McMarr P. J., and Lawrence R. K. “Relationship Between Oxide Density and Charge Trapping in SiO Films”, J. Appl. Phys., Vol. 85, p. 6577, 1999.
6. Griscom D. L. “Defects in Amorphous Insulators”, J. Non-Crystalline Solids, Vol. 31, p. 241, 1978.
7. Warren W. L., Shaneyfelt M. R., Fleetwood D. M., Schwank J. R., Winokur P. S., and Devine R. A. B. “Microscopic Nature of Border Traps in MOS Oxides”, IEEE Trans. Nucl. Sci., Vol. 41, p. 1817, 1994.
8. Devine R. A. B. “Oxygen Gettering and Oxide Degradation During Annealing of Si/SiO/Si Structures”, J. Appl. Phys., Vol. 77, p. 175, 1995.
9. Snow E. H., Grove A. S., and Fitzgerald D. J. “Effect of Ionization Radiation on Oxidized Silicon Surfaces and Planar Devices”, Proc. of IEEE, 55(7), 1168 (1969).
10. Moskovskaya Y. M., Belostotskaya S. O., Fedorov R. A., Rudakov G.A., Bobrovskiy D. V., Nikiforov A. Yu., Ula¬nova A. V., Sorokoumov G. S. “Modification of CMOS Process Route With the Aim of Increasing Total Ionizing Dose Hardness” // Nanoindustry. Special issue (74) 2017, P. 206–212.
11. Boychenko D. V., Kalashnikov O. A., Ni¬ki¬fo¬rov A. Y., Ulanova A. V., Bob¬rov¬sky D. V., Nekrasov P. V. “Total Ionizing Dose Effects and Radiation Testing of Complex Multifunctional VLSI Devices”. Facta Universitatis Electronics and Energetics, Vol. 28, № 1, pp. 153–164, 2015.
12. Kalashnikov O. A., and Nikiforov A. Y. “TID Behavior of Complex Multifunctional VLSI Devices”, in Proc. of 29th Int. Conf. on Microelectronics, MIEL 2014, Belgrade, Serbia, May 2014,
pp. 455–458.
13. Sogoyan A., Artamonov A., Nikiforov A., Boychenko D. “Method for Integrated Circuits Total Ionizing Dose Hardness Testing Based on Combined Gamma- and x-ray Irradiation Facilities”, Facta Universitatis — Series: Electronics and Energetics 2014. Volume 27, Issue 3, P. 329–338.
14. Boychenko D. V., Kalashnikov O. A., Ka¬ra¬ko¬zov A. B., and Nikiforov A. Y. “Rational Methodological Approach to Evaluation of Dose Resistance of CMOS Microcircuits with Respect to Low Intensity Effects”, Russian Microelectronics, Vol. 44, No. 1, pp. 1–7, 2015.
15. Sorokoumov G. S., Bobrovskiy D. V., Ka¬¬lash¬nikov O. A., Ulanova A. V., and Mos¬kov¬s-kaya Y. M. “NI PXI-based Automated Measurement System for Digital ASICs Verification”, MATEC Web of Conferences, Vol. 79, article number 01059,
2016.
CMOS ICs are widely used in on-board systems with radiation hardness requirements, that’s why the total ionizing dose (TID) provision within IC design and manufacturing process is a relevant task. Although almost all contemporary publications on TID effects correspond to deep submicron VLSI circuits, according to the authors’ practical experience the majority of ICs used for space applications are manufactured nowadays in the basis of 0.8–5µm design rules and processes. The issues of the impact of the process parameters on CMOS IC TID hardness threshold are widely discussed in literature [1–10]. However, the previously published papers deal with the 20–30-year old processes, and their equivalence with up-to-date processes is not obvious. Therefore the research of the typical space application oriented micron CMOS process parameters influence on their TID threshold seems to be useful. First of all, the obtained results will make it possible to evaluate the equivalence of dominant TID effects and fault mechanisms of up-to-date process to previously investigated processes. Secondly, it gives us useful experience of refining the methodology for CMOS process characterization based on TID hardness levels. And lastly, it will help us to choose parameters rational values for obtaining a compromise between IC (product) functionality and radiation hardness level.
It is well known that TID hardness threshold depends heavily on gate insulator thickness and growth process parameters, in particular on temperature and chemical oxidization environment [1–5]. It is assumed that the oxide growing temperature for TID hardness provision should be within the range of 850–925 °C. Annealing processes conducted under temperatures higher than 950 °C significantly degrade CMOS IC TID hardness [1, 2].
The maximum temperature of the further operations should not exceed the gate oxide growing process temperature [6, 7].
To a lesser extent, TID hardness level is dependent on the atmosphere of oxide growing process [9]. However, it has been experimentally established that wet oxidization in water vapors results in a decrease in total TID-induced charge, which may indicate a decreased number of traps, and thus indicate an increase in TID hardness [10].
So we decided to compare TID hardness of several standard process route versions of micron CMOS IC using test chip samples meant for space systems applications and provided by a typical ASIC designer and manufacturer company.
RADIATIONAL EXPERIMENT DESCRIPTION
A specialized test 5503 series IC gate array manufactured by SMC “Technological Centre” (1.5µm design rules, gate oxide thickness of 325Å) was chosen as the “device under test” (DUT). The test microcircuit included the set of inverter chains and simple logic circuits. IC dies were manufactured utilizing three technological process flow modifications (see Table 1).
The research was performed using 10keV X-ray tester [11] as a radiation source. TID value measurement was performed using BKRI dosimeter with an additional calibration by TID effect equivalence criteria using the linear electron accelerator in bremsstrahlung generation mode (NRNU MEPHI and SPELS Radiation Test Center, Moscow, Russia) [12,13]. The test dose rate was about 10–100rad/s and it has been established that there were no essential dose-rate effects in the used dose rate range [14].
The scheduling of ICs operation modes as well as electrical parameter measurements and functional control and testing during the irradiation were performed with the National Instruments PXI-based hardware and LabVIEW graphical programming environment [15].
TID hardness dependencies of all radiation-sensitive parameters according to the specification such as — static power supply current, low and high output voltages, propagation delay and functional operability — have been measured in every TID point for every IC sample in the experiment.
The previously obtained TID test results of DUT samples from 10 previously manufactured standard process flow lots have been analyzed. It appeared that the static power supply current was the most radiation sensitive parameter.
The typical (average) TID threshold value based on the criteria of power supply current degradation was about 150krad. The TID degradation threshold determined with the functional operability criteria was found to be about 260krad at Ucc = 4.5V and 310krad at Ucc = 5.5V. And the TID threshold of low and high output voltages was 390 krad at Ucc = 4.5V and 5.5V.
Therefore current vs. TID dependencies in standard process route were used as the gold-device reference base for further comparison.
EXPERIMENTAL RESULTS
Figures 1 and 2 present the comparative power supply current vs. dose dependencies for ICs manufactured in standard and modified process routes. It has been established that the power supply current value does not go beyond the values mentioned in technical specifications (400µA) for all process flow modifications up to maximum obtained TID of 3Mrad, whereas for ICs based on the standard process route the TID failure threshold in terms of power supply current was visible at 130 to 170krad.
The results of comparative research into dose sensitivity of different process flow modifications have demonstrated that the best radhard characteristics can be achieved combining 700 °С temperature and oxide growing process in wet atmosphere based on steam generator (Sample 3). The maximum value of power supply current corresponds to oxidization temperature 900 °С and dry oxide (Sample 2). Samples manufactured with oxidization temperature 850 °С and dry oxide, take an intermediate position. It should be noted that the maximum power supply current values were only thrice as large as maximum allowed value for all modified processes.
Thus, decreasing the gate oxide growing temperature from 1000 °С to 900 °С leads to power supply current decrease from hundreds of µA up to units of µA for the TID level of 130krad, leading to CMOS IC hardness threshold increase by an order of magnitude. The further temperature cool-down up to 850 °С leads to negligible reduction in current vs. TID sensitivity: from 3.33µА (900 °С) down to 2.63µА (850 °С) at TID level 1Mrad. The change to the wet oxidization while further oxide growing temperature cool-down up to 700 °С results in TID sensitivity decrease approximately by half, the current being equal to 1.43µА at corresponding dose of 1Mrad.
CONCLUSIONS
It has been experimentally established that for CMOS processes with the gate oxide thickness equal to 325Å the TID hardness is ensured by the gate oxide growth temperature of 850–900 °C, provided that the maximum temperature of the further operations does not exceed the gate oxide growing process temperature. The oxidization in wet environment can reduce the gate oxide growing process temperature up to 700 °C, leading to a decrease in power supply current vs. TID sensitivity, but in this case the reliability of ICs and stability of their electrophysical properties have to be confirmed.
REFERENCES
1. Dawes W. R., Jr., Dervenwick G. F., and Gregory B. L. “Process Technology for Radiation-hardened CMOS Integrated Circuits” // IEEE J Solid-State Circuits. 1976. SC-11, 4.
2. Dressendorfer P. V. “Radiation-Hardening Technology”, in Radiation Effects in MOS Devices and Circuits, Edited by T-P. Ma and Dressendorfer P. V. (Wiley, New York, 1989), pp. 333–400.
3. Shaneyfelt M. R., Schwank J. R., Fleetwood D. M., Winokur P. S., Hughes K. L., Hash G. L. and Connors M. P. “Interface-trap Buildup Rates in Wet and Dry Oxides”, IEEE Trans. Nucl. Sci., Vol. 39, № 6, pp. 2244–2251, 1992.
4. daSilva E. F., Nishioka Y., and Ma T.-P. “Effects of Trichloroethane During Oxide Growth on Radiation-Induced Interface Traps in Metal/SiO /Si Capacitors”, Appl. Phys. Lett., Vol. 51, p. 1262, 1987.
5. Mrstik B. J., Afanas’ev V. V., Stesmans A., McMarr P. J., and Lawrence R. K. “Relationship Between Oxide Density and Charge Trapping in SiO Films”, J. Appl. Phys., Vol. 85, p. 6577, 1999.
6. Griscom D. L. “Defects in Amorphous Insulators”, J. Non-Crystalline Solids, Vol. 31, p. 241, 1978.
7. Warren W. L., Shaneyfelt M. R., Fleetwood D. M., Schwank J. R., Winokur P. S., and Devine R. A. B. “Microscopic Nature of Border Traps in MOS Oxides”, IEEE Trans. Nucl. Sci., Vol. 41, p. 1817, 1994.
8. Devine R. A. B. “Oxygen Gettering and Oxide Degradation During Annealing of Si/SiO/Si Structures”, J. Appl. Phys., Vol. 77, p. 175, 1995.
9. Snow E. H., Grove A. S., and Fitzgerald D. J. “Effect of Ionization Radiation on Oxidized Silicon Surfaces and Planar Devices”, Proc. of IEEE, 55(7), 1168 (1969).
10. Moskovskaya Y. M., Belostotskaya S. O., Fedorov R. A., Rudakov G.A., Bobrovskiy D. V., Nikiforov A. Yu., Ula¬nova A. V., Sorokoumov G. S. “Modification of CMOS Process Route With the Aim of Increasing Total Ionizing Dose Hardness” // Nanoindustry. Special issue (74) 2017, P. 206–212.
11. Boychenko D. V., Kalashnikov O. A., Ni¬ki¬fo¬rov A. Y., Ulanova A. V., Bob¬rov¬sky D. V., Nekrasov P. V. “Total Ionizing Dose Effects and Radiation Testing of Complex Multifunctional VLSI Devices”. Facta Universitatis Electronics and Energetics, Vol. 28, № 1, pp. 153–164, 2015.
12. Kalashnikov O. A., and Nikiforov A. Y. “TID Behavior of Complex Multifunctional VLSI Devices”, in Proc. of 29th Int. Conf. on Microelectronics, MIEL 2014, Belgrade, Serbia, May 2014,
pp. 455–458.
13. Sogoyan A., Artamonov A., Nikiforov A., Boychenko D. “Method for Integrated Circuits Total Ionizing Dose Hardness Testing Based on Combined Gamma- and x-ray Irradiation Facilities”, Facta Universitatis — Series: Electronics and Energetics 2014. Volume 27, Issue 3, P. 329–338.
14. Boychenko D. V., Kalashnikov O. A., Ka¬ra¬ko¬zov A. B., and Nikiforov A. Y. “Rational Methodological Approach to Evaluation of Dose Resistance of CMOS Microcircuits with Respect to Low Intensity Effects”, Russian Microelectronics, Vol. 44, No. 1, pp. 1–7, 2015.
15. Sorokoumov G. S., Bobrovskiy D. V., Ka¬¬lash¬nikov O. A., Ulanova A. V., and Mos¬kov¬s-kaya Y. M. “NI PXI-based Automated Measurement System for Digital ASICs Verification”, MATEC Web of Conferences, Vol. 79, article number 01059,
2016.
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