rus
Issue #9/2018
Baranov Yuriy N., Schwartz Karl-Heinrich M., Sokolov Evgeniy M., Statsenko Vladimir N., Fedotov Sergey D., Tarasov Dmitry V., Timoshenkov Sergey P.
Atmospheric Pressure Chloride Transport in Epitaxial System
Atmospheric Pressure Chloride Transport in Epitaxial System
The paper presents the results of development and studies of the epitaxial silicon layers formation obtained by using a chloride gas transport (CVT) in the sandwich system. It deals with the formation of single- and polycrystalline layers on different silicon substrates as well as on epitaxial wafers of “silicon with dielectric isolation” (EPIC). We have researched the temperature distribution in the sandwich system and the thickness of epitaxial layer at the area of substrates, as well as the dependence of layer growth rate to the temperature of source-wafer and substrate, Cl/H ratio and magnitude of the gap between wafers in the sandwich system. The growth rate of polycrystalline layers on EPIC reaches 12µm/min when the thickness of layers is 300–600µm, of single-crystal Si layers on a silicon wafer being 8–10µm/min when the thickness of layers is 40–100µm. The most significant feature of CVT process from a practical point of view is that during the formation of epitaxial layers as a source of silicon, we can use discarded wafers and structures after various cycles of epitaxial fabrication. The transfer mechanism allows creating single crystal epitaxial layers with a growth rate about 10µm/min, regardless of the source-wafer structural quality and polycrystalline support layers, which significantly reduces the cost of manufacturing process.
Теги: chloride vapor transport cvt epic gas-transport epitaxy mems polycrystalline silicon sandwich-system single crystalline silicon газотранспортная эпитаксия газотранспортный перенос ксди монокристаллический кремний мэмс поликристаллический кремний сэндвич-система хлоридный процесс
Currently the process of forming epitaxial layers of silicon has been studied thoroughly enough [1]. There are various methods of forming silicon epitaxial layers, and among microelectronic technologies we can highlight the method of chemical vapor deposition (CVD) as most common for the industrial production of Si-layers. Operating temperatures of CVD process are in the range of 200 °C (PECVD) up to 1200 °C (APCVD) and the growth rate can reach 10µm/min (RTCVD) [2]. The main advantages of the CVD method are high performance and simplicity of execution. Standard vertical reactor allows forming silicon layers with thickness up to 150µm on 14pcs of 6-inch substrates or 5pcs of 8-inch substrates. Horizontal type reactor allows forming silicon layers with thickness up to 100µm on 5 pcs of 8-inch substrates with better thickness and resistivity uniformity. However there are several technological problems in case of manufacturing thick silicon epitaxial layers (up to 150µm) for power electronics [3] or back-up polycrystalline layers (thickness up to 400µm) for EPIC structures for MEMS [4–5]. These issues include: rapid overgrowth of the reactor internal surfaces, increased consumption of silicon-containing reagents and process duration. Epitaxial growth of thick epitaxial layers by CVD is not economically advantageous due to elevated consumption of power and expensive reagents. High sensitivity of the process to contamination leads to an increase in discarded wafers due to overgrowth of the reactor internal surfaces. Therefore the growing of thick epitaxial silicon layers requires a new alternative method of epitaxy combining high performance and low cost of the fabrication process.
The report presents the results of research into silicon gas-transport epitaxy carried out by transferring silicon atoms from a solid source through gaseous silicon halogenides to a substrate at atmospheric pressure [6]. Recently a method of silicon iodide gas transportation at atmospheric pressure (APIVT, atmospheric pressure iodine vapor transport) [7] has been studied. This method is based on reaction of Sil2 disproportionation [8] and is used for growing silicon layers for solar cells and other photovoltaic devices. The maximum growth rate of the polysilicon layer with a crystal grain size of 5–20μm is 3μm/min, the growth temperature range being 750–950 °C [9]. The authors [10] have noted that silicon of lower quality can be used as a source material (with higher content of impurities) instead of single crystal silicon substrate. The free energies of formation of silicon halide compounds and halide impurities are different, which makes it possible to purify silicon during epitaxy. Using APIVT for growing the polysilicon layers has several advantages, but there is no information on the applicability of this method to the growth of single crystal layers. Also, the use of gaseous silicon iodides in microelectronics is complicated, because there is no available manufacturer of initial reagents.
Our method is based on the same principles as APIVT but contains some significant features. Silicon mass transport occurs in a chloride-containing atmosphere of special sandwich system [6]. This system provides low cost manufacturing process due to inexpensive material (discarded Si wafers) and low flow rates of gaseous reactants. Another advantage of chloride vapor transport (CVT) in sandwich system is high growth rate of polycrystalline and epitaxial layers.
The main aim of our study was to determine the basic technological dependencies in Si-H-Cl system. In order to achieve this aim we used Lever thermodynamic model [11]. This model describes the Si-H-Cl system by considering the combination of nine components: H2, HCl, SiCl, SiCl2, SiCl4, SiHCl3, SiH2Cl2, SiH3Cl and SiH4 in the temperature range 800–1700 °K. One may plot lines of constant Si/Cl ratio on a plot of Cl/H versus temperature, as shown in Fig. 1. Thus the initial parameters of the technological process can be selected by means of Lever nomogram, the upper left corner being dominated by SiHCl3.
Dramatically increasing dependence in the upper right corner is due to increased amounts of SiCl2 while the effect of very high Cl/H ratios at temperatures below 1200°K leads to an increase in SiCl4 at the expense of SiHCl3. If we use SiCl4 as the source of Si and Cl, then the Si/Cl ratio is necessarily 0.25. In this case, operating points above the shaded line will result in etching, not growth. Also it may be noted that if SiHCl3 is used as starting material, etching could occur only at very high Cl/H ratios and temperatures above 1500°K.
Using this nomogram a process of gas transport epitaxial silicon deposition in various ambiences: HCl + H2 and SiCl4+ H2, has been investigated. A method has also been developed for the gas-transport silicon epitaxy in sandwich system [6], where the transfer of silicon atoms occurs between two wafers which are placed opposite each other with a small gap. One of them is the source and the other is the substrate.
In Fig. 2, the large “valley” to the lower right, indicating a low Si/Cl ratio, is due to the predominance of HC1, while the broad ridge on the left is dominated by SiHC13.
One of implementations of this method is shown in Fig. 1, where 1 is reaction chamber; 2 — RF coil; 3 — graphite susceptor covered with SiC for Si source wafer. Source Si wafer is located on graphite susceptor covered with SiC. The RF coil is placed around the reaction chamber. The silicon substrate or EPIC wafer is placed above the source wafer. The gap between substrate and source wafer is regulated via substrate position. The temperature gradient between source and substrate is influencing the gap. The total pressure in reactor chamber was 1 atm. Dry hydrogen (the vapor water content <5ppb) was used as carrier gas. Pure hydrogen chloride (HC1) diluted by hydrogen is used as vapor transport agent.
Inside the reaction chamber the source is located on a hot susceptor and the substrate is on a graphite screen above the source. Thus, a temperature and concentration gradient is created between two wafers which ensures the gas transport reaction.
The temperature-flow-time diagram of CVT process in sandwich system is shown in Fig. 3. After loading the substrates the reaction chamber is purged by N2 and H2 at first interval. After that the susceptor is heated up to ~1200 °C. HC1 gas diluted by hydrogen is supplied to reaction chamber. After the deposition of desired layer thickness is completed the system is purged by pure H2 and cooled down.
Polycrystalline (poly-Si) and epitaxial (epi-Si) silicon layers were deposited on EPIC (Epitaxial Process for Insulated Circuits) wafers and silicon substrates by CVT method in sandwich system.
The main results of this investigation are shown in. Figs. 4–6. First we have studied the dependence of temperature gradient between source and substrate in the sandwich system on the gap size (Fig. 4a) and the influence of gap size on the deposition rate of Si-epi at C1/H = 0.1 (Fig. 4b). The temperature gradient was controlled via optical pyrometer. The layer thickness was measured by IR Fourier spectroscopy (spectrometer FSM 1201, Infraspeck Ltd., Russia). Silicon wafers with ∅100mm, antimony doping, resistivity 0.01Ω∙cm and orientation (111) with 4° misorientation were used as Si-source wafers. Silicon wafers with ∅100mm, boron doping, resistivity 10Ω∙cm and orientation (111) were used as substrate wafers.
The results on Fig. 4 indicate that with increasing gap size the temperature gradient between two wafers increases while the growth rate decreases, allowing us to determine the optimum range of gap size 0.2–1mm. It should be noted that the presence of quartz screen above the substrate leads to the value of temperature gradient about 80–100 °C at 3–4mm gap. This fact means that we have an additional opportunity to operate the process of silicon deposition.
Fig. 5 shows the main dependences of growth process on Cl/H ratio and gap size at 1250 °C for different ambiences, where (a) — HC1 + H2, (b) — SiCl4 + H2, (c) — different ambiences at different gaps; (d) — dependence of the average deposition rate on the temperature of the source.
We have determined that the highest rate of growth can be obtained using HCl+H2 gas-vapor mixture with 0.3mm gap. Also we have found that the growth rate of silicon layer is increased with increasing Cl/H ratio and growth temperature. The dependences are in line with the data of Lever nomogram. It should be noted that all results (Fig. 5) mentioned above were obtained in sandwich system without any screens on substrate. When screen is used above the substrate the principal dependences are the same, but the deposition rate is increased due to the temperature gradient decrease. In addition, an increase in deposition rate depends on the screen properties. The results have proved that to obtain the same deposition rate we have to keep the same temperature gradient and Cl/H ratio. These experiments are in progress.
Fig. 6 shows the summarized results of our investigations including poly-Si deposition on EPIC substrates and single-Si deposition on silicon wafers.
In the presented results the growth rate of the polycrystalline layers is 12µm/min when the thickness of the layers is 300–600 microns. The growth rate of the monocrystalline Si layers was varied in the range of 1–8µm/min, thus the resulting thickness of the layers was between 40 and 100 microns. The thickness uniformity of layer was not more than 10 %, and the deviation of resistivity from average value on wafer area is not more than 15 %. It has been found that the decrease of the gap of 0.1mm significantly increases the growth rate of polycrystalline Si layers which is not observed in the case of monocrystalline Si.
Concerning the quality of single crystal silicon layers we should note that the main defects of layers are stacking faults, the density of these defects being about 3–5cm−2 (Fig. 7). The density of structural defects on the epi-wafer surface was counted via the optical microscope Leitz (Germany). In our opinion, the origin of stacking faults is the residual natural oxide or the vapor products of oxide removal during a baking step or the low-temperature defect of Si (111) with 4° misorientation.
The research has resulted in the CVT reactor concept (Fig. 8) and a new design of reaction chamber (Fig. 8a).
The authors consider the following points and results of the research as novel: chloride vapor transport deposition in sandwich system for poly-Si and epi-Si layers was investigated for the first time. It has been found that the main parameters which influence the deposition rate of silicon layers are the source temperature, the gap between source and substrate and the Cl/H ratio. The deposition rate of poly-Si layers on EPIC wafers and epi-Si layers on silicon substrates were over 10μm/min for poly-Si and 6–10μm/min for epi-Si at optimal Cl/H ratio and gap width. The density of stacking faults as the main defect of these layers was 3–5cm−2. Consequently, the advantages of CVT process are low cost (as discarded epitaxial wafers might be used as low cost silicon source for poly-Si deposition) and high growth rate of silicon layers. The resistivity of obtained silicon layers is the same as that of one of initial source wafers, so we need to replace the initial source wafer to change the resistivity. But when we deposit polysilicon layers on EPIC substrates the resistivity is not a problem. The commercial concept of CVT reactor was designed as a result of the sandwich system investigation.
We would like to express sincere thanks to A. F. Volkov (Epiel JSC) for his significant contribution to the development of the CVT method.
This work was partially supported by the Russian Science Foundation. Unique identifier for applied research is 16-19-00177 “Investigation and design of smart MEMS sensors with self-calibration function and automated test system” (2016–2017).
REFERENCES
1. Fisher G.,Seacrist M. R., Standley R. W. Silicon Crystal Growth and Wafer Technologies // Proceedings of the IEEE, Vol. 100, 2012, P. 1454–1474.
2. Faller F. R., Henninger V., Hurrle A., Schillinger N. “Optimization of the CVD Process for Low-cost Crystalline-Silicon Thin-Film Solar Cells”. The 2nd World Conference on PV Solar Energy Conversion, Vienna, P. 1278, (1998).
3. Rosa M. Thick Epitaxial Silicon Enhances Performance of Power and Mems Devices // Nanochip FAB Solution (Applied Materials), 2014, Vol. 9, Iss. 1, P. 24–29.
4. Ng E. J., Wang S., Buchman D., Chiang C.-F., Kenny T., Muenzel H., Fuertsch M., Marek J., Gomez U., Yama G. and OʼBrien G. Ultra-Stable Epitaxial Polysilicon Resonators // Solid-State Sensors, Actuators, and Microsystems Workshop Hilton Head Island, South Carolina, June 3–7, 2012, P. 271–274.
5. Yasaitis J., Judy M., Brosnihan T., Garone P., Pokrovskiy N., Sniderman D., Limb S., Howe R., Boser B., Palaniapan M., Jiang X. and Bhave S. A Modular Process for Integrating Thick Polysilicon MEMS Devices with Sub-Micron CMOS // Micromachining and Microfabrication Process Technology VIII, Proceedings of SPIE, Vol. 4979 (2003), P. 145–154.
6. Patent RU2393585 “Method of Semiconductor Structure Formation” app. date 28.04.2009, publ. date 27.06.2010. (In Russian).
7. Wang T. H. and Ciszek T. F. Growth of Large-Grain Silicon Layers by Atmospheric Iodine Vapor Transport // J. Electrochem. Society, 2000, Vol. 147, No. 5, P. 1945–1949.
8. Glang R. and Wajda E. S. “Silicon” in The Art and Science of Growing Crystals, Ed. J. J. Gilman, John Wiley & Sons, New York, P. 80–92, (1963).
9. Wang T. H., Ciszek T. F., Page M. R., Bauer R. E., Wang Q. and Landry M. D. “APIVT-Grown Silicon Thin Layers and PV Devices” to be presented at the 29th IEEE PV Specialists Conference, New Orleans, Louisiana, May 20–24, 2002, NREL/CP-520-31441
10. Ciszek T. F., Wang T. H., Page M. R., Menna P., Bauer R. E., Good E. A. and Landry M. D. “Alternative Solar-Grade Silicon Feedstock Approaches” to be presented at the NCPV Program Review Meeting Lakewood, Colorado, 14–17 October 2001, NREL/CP-520-31007.
11. Lever R. F. The Equilibrium Behavior of the Silicon-Hydrogen-Chlorine system // IBM Journal, Sept. 1964, P. 460–465.
The report presents the results of research into silicon gas-transport epitaxy carried out by transferring silicon atoms from a solid source through gaseous silicon halogenides to a substrate at atmospheric pressure [6]. Recently a method of silicon iodide gas transportation at atmospheric pressure (APIVT, atmospheric pressure iodine vapor transport) [7] has been studied. This method is based on reaction of Sil2 disproportionation [8] and is used for growing silicon layers for solar cells and other photovoltaic devices. The maximum growth rate of the polysilicon layer with a crystal grain size of 5–20μm is 3μm/min, the growth temperature range being 750–950 °C [9]. The authors [10] have noted that silicon of lower quality can be used as a source material (with higher content of impurities) instead of single crystal silicon substrate. The free energies of formation of silicon halide compounds and halide impurities are different, which makes it possible to purify silicon during epitaxy. Using APIVT for growing the polysilicon layers has several advantages, but there is no information on the applicability of this method to the growth of single crystal layers. Also, the use of gaseous silicon iodides in microelectronics is complicated, because there is no available manufacturer of initial reagents.
Our method is based on the same principles as APIVT but contains some significant features. Silicon mass transport occurs in a chloride-containing atmosphere of special sandwich system [6]. This system provides low cost manufacturing process due to inexpensive material (discarded Si wafers) and low flow rates of gaseous reactants. Another advantage of chloride vapor transport (CVT) in sandwich system is high growth rate of polycrystalline and epitaxial layers.
The main aim of our study was to determine the basic technological dependencies in Si-H-Cl system. In order to achieve this aim we used Lever thermodynamic model [11]. This model describes the Si-H-Cl system by considering the combination of nine components: H2, HCl, SiCl, SiCl2, SiCl4, SiHCl3, SiH2Cl2, SiH3Cl and SiH4 in the temperature range 800–1700 °K. One may plot lines of constant Si/Cl ratio on a plot of Cl/H versus temperature, as shown in Fig. 1. Thus the initial parameters of the technological process can be selected by means of Lever nomogram, the upper left corner being dominated by SiHCl3.
Dramatically increasing dependence in the upper right corner is due to increased amounts of SiCl2 while the effect of very high Cl/H ratios at temperatures below 1200°K leads to an increase in SiCl4 at the expense of SiHCl3. If we use SiCl4 as the source of Si and Cl, then the Si/Cl ratio is necessarily 0.25. In this case, operating points above the shaded line will result in etching, not growth. Also it may be noted that if SiHCl3 is used as starting material, etching could occur only at very high Cl/H ratios and temperatures above 1500°K.
Using this nomogram a process of gas transport epitaxial silicon deposition in various ambiences: HCl + H2 and SiCl4+ H2, has been investigated. A method has also been developed for the gas-transport silicon epitaxy in sandwich system [6], where the transfer of silicon atoms occurs between two wafers which are placed opposite each other with a small gap. One of them is the source and the other is the substrate.
In Fig. 2, the large “valley” to the lower right, indicating a low Si/Cl ratio, is due to the predominance of HC1, while the broad ridge on the left is dominated by SiHC13.
One of implementations of this method is shown in Fig. 1, where 1 is reaction chamber; 2 — RF coil; 3 — graphite susceptor covered with SiC for Si source wafer. Source Si wafer is located on graphite susceptor covered with SiC. The RF coil is placed around the reaction chamber. The silicon substrate or EPIC wafer is placed above the source wafer. The gap between substrate and source wafer is regulated via substrate position. The temperature gradient between source and substrate is influencing the gap. The total pressure in reactor chamber was 1 atm. Dry hydrogen (the vapor water content <5ppb) was used as carrier gas. Pure hydrogen chloride (HC1) diluted by hydrogen is used as vapor transport agent.
Inside the reaction chamber the source is located on a hot susceptor and the substrate is on a graphite screen above the source. Thus, a temperature and concentration gradient is created between two wafers which ensures the gas transport reaction.
The temperature-flow-time diagram of CVT process in sandwich system is shown in Fig. 3. After loading the substrates the reaction chamber is purged by N2 and H2 at first interval. After that the susceptor is heated up to ~1200 °C. HC1 gas diluted by hydrogen is supplied to reaction chamber. After the deposition of desired layer thickness is completed the system is purged by pure H2 and cooled down.
Polycrystalline (poly-Si) and epitaxial (epi-Si) silicon layers were deposited on EPIC (Epitaxial Process for Insulated Circuits) wafers and silicon substrates by CVT method in sandwich system.
The main results of this investigation are shown in. Figs. 4–6. First we have studied the dependence of temperature gradient between source and substrate in the sandwich system on the gap size (Fig. 4a) and the influence of gap size on the deposition rate of Si-epi at C1/H = 0.1 (Fig. 4b). The temperature gradient was controlled via optical pyrometer. The layer thickness was measured by IR Fourier spectroscopy (spectrometer FSM 1201, Infraspeck Ltd., Russia). Silicon wafers with ∅100mm, antimony doping, resistivity 0.01Ω∙cm and orientation (111) with 4° misorientation were used as Si-source wafers. Silicon wafers with ∅100mm, boron doping, resistivity 10Ω∙cm and orientation (111) were used as substrate wafers.
The results on Fig. 4 indicate that with increasing gap size the temperature gradient between two wafers increases while the growth rate decreases, allowing us to determine the optimum range of gap size 0.2–1mm. It should be noted that the presence of quartz screen above the substrate leads to the value of temperature gradient about 80–100 °C at 3–4mm gap. This fact means that we have an additional opportunity to operate the process of silicon deposition.
Fig. 5 shows the main dependences of growth process on Cl/H ratio and gap size at 1250 °C for different ambiences, where (a) — HC1 + H2, (b) — SiCl4 + H2, (c) — different ambiences at different gaps; (d) — dependence of the average deposition rate on the temperature of the source.
We have determined that the highest rate of growth can be obtained using HCl+H2 gas-vapor mixture with 0.3mm gap. Also we have found that the growth rate of silicon layer is increased with increasing Cl/H ratio and growth temperature. The dependences are in line with the data of Lever nomogram. It should be noted that all results (Fig. 5) mentioned above were obtained in sandwich system without any screens on substrate. When screen is used above the substrate the principal dependences are the same, but the deposition rate is increased due to the temperature gradient decrease. In addition, an increase in deposition rate depends on the screen properties. The results have proved that to obtain the same deposition rate we have to keep the same temperature gradient and Cl/H ratio. These experiments are in progress.
Fig. 6 shows the summarized results of our investigations including poly-Si deposition on EPIC substrates and single-Si deposition on silicon wafers.
In the presented results the growth rate of the polycrystalline layers is 12µm/min when the thickness of the layers is 300–600 microns. The growth rate of the monocrystalline Si layers was varied in the range of 1–8µm/min, thus the resulting thickness of the layers was between 40 and 100 microns. The thickness uniformity of layer was not more than 10 %, and the deviation of resistivity from average value on wafer area is not more than 15 %. It has been found that the decrease of the gap of 0.1mm significantly increases the growth rate of polycrystalline Si layers which is not observed in the case of monocrystalline Si.
Concerning the quality of single crystal silicon layers we should note that the main defects of layers are stacking faults, the density of these defects being about 3–5cm−2 (Fig. 7). The density of structural defects on the epi-wafer surface was counted via the optical microscope Leitz (Germany). In our opinion, the origin of stacking faults is the residual natural oxide or the vapor products of oxide removal during a baking step or the low-temperature defect of Si (111) with 4° misorientation.
The research has resulted in the CVT reactor concept (Fig. 8) and a new design of reaction chamber (Fig. 8a).
The authors consider the following points and results of the research as novel: chloride vapor transport deposition in sandwich system for poly-Si and epi-Si layers was investigated for the first time. It has been found that the main parameters which influence the deposition rate of silicon layers are the source temperature, the gap between source and substrate and the Cl/H ratio. The deposition rate of poly-Si layers on EPIC wafers and epi-Si layers on silicon substrates were over 10μm/min for poly-Si and 6–10μm/min for epi-Si at optimal Cl/H ratio and gap width. The density of stacking faults as the main defect of these layers was 3–5cm−2. Consequently, the advantages of CVT process are low cost (as discarded epitaxial wafers might be used as low cost silicon source for poly-Si deposition) and high growth rate of silicon layers. The resistivity of obtained silicon layers is the same as that of one of initial source wafers, so we need to replace the initial source wafer to change the resistivity. But when we deposit polysilicon layers on EPIC substrates the resistivity is not a problem. The commercial concept of CVT reactor was designed as a result of the sandwich system investigation.
We would like to express sincere thanks to A. F. Volkov (Epiel JSC) for his significant contribution to the development of the CVT method.
This work was partially supported by the Russian Science Foundation. Unique identifier for applied research is 16-19-00177 “Investigation and design of smart MEMS sensors with self-calibration function and automated test system” (2016–2017).
REFERENCES
1. Fisher G.,Seacrist M. R., Standley R. W. Silicon Crystal Growth and Wafer Technologies // Proceedings of the IEEE, Vol. 100, 2012, P. 1454–1474.
2. Faller F. R., Henninger V., Hurrle A., Schillinger N. “Optimization of the CVD Process for Low-cost Crystalline-Silicon Thin-Film Solar Cells”. The 2nd World Conference on PV Solar Energy Conversion, Vienna, P. 1278, (1998).
3. Rosa M. Thick Epitaxial Silicon Enhances Performance of Power and Mems Devices // Nanochip FAB Solution (Applied Materials), 2014, Vol. 9, Iss. 1, P. 24–29.
4. Ng E. J., Wang S., Buchman D., Chiang C.-F., Kenny T., Muenzel H., Fuertsch M., Marek J., Gomez U., Yama G. and OʼBrien G. Ultra-Stable Epitaxial Polysilicon Resonators // Solid-State Sensors, Actuators, and Microsystems Workshop Hilton Head Island, South Carolina, June 3–7, 2012, P. 271–274.
5. Yasaitis J., Judy M., Brosnihan T., Garone P., Pokrovskiy N., Sniderman D., Limb S., Howe R., Boser B., Palaniapan M., Jiang X. and Bhave S. A Modular Process for Integrating Thick Polysilicon MEMS Devices with Sub-Micron CMOS // Micromachining and Microfabrication Process Technology VIII, Proceedings of SPIE, Vol. 4979 (2003), P. 145–154.
6. Patent RU2393585 “Method of Semiconductor Structure Formation” app. date 28.04.2009, publ. date 27.06.2010. (In Russian).
7. Wang T. H. and Ciszek T. F. Growth of Large-Grain Silicon Layers by Atmospheric Iodine Vapor Transport // J. Electrochem. Society, 2000, Vol. 147, No. 5, P. 1945–1949.
8. Glang R. and Wajda E. S. “Silicon” in The Art and Science of Growing Crystals, Ed. J. J. Gilman, John Wiley & Sons, New York, P. 80–92, (1963).
9. Wang T. H., Ciszek T. F., Page M. R., Bauer R. E., Wang Q. and Landry M. D. “APIVT-Grown Silicon Thin Layers and PV Devices” to be presented at the 29th IEEE PV Specialists Conference, New Orleans, Louisiana, May 20–24, 2002, NREL/CP-520-31441
10. Ciszek T. F., Wang T. H., Page M. R., Menna P., Bauer R. E., Good E. A. and Landry M. D. “Alternative Solar-Grade Silicon Feedstock Approaches” to be presented at the NCPV Program Review Meeting Lakewood, Colorado, 14–17 October 2001, NREL/CP-520-31007.
11. Lever R. F. The Equilibrium Behavior of the Silicon-Hydrogen-Chlorine system // IBM Journal, Sept. 1964, P. 460–465.
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