rus
Issue #9/2018
Kulikov Dmitry V., Savelyev Denis I.
Features of Mismatch Eff ects on Parameters of High-Speed Time-Interleaved Multichannel ADCs
Features of Mismatch Eff ects on Parameters of High-Speed Time-Interleaved Multichannel ADCs
The paper is devoted to special types of distortions in the spectrum of output signal of multichannel ADCs caused by mismatch of parameters of the channels used. The influence of the factors limiting the achievement of high dynamic characteristics has been investigated
INTRODUCTION
Modern electronics cannot do without high-performance analog-to-digital converters (ADC), because in signal processing systems ever more frequently direct signal processing at high frequencies is used without transferring signal spectrum to low frequencies region.
To decrease performance requirements for stages of high performance ADC, time-interleaved multichannel pipeline architecture has been used [1, 2], that is with partial overlapping of cycles of those channels that operate in parallel (see Fig. 1). Such architecture enables attaining high resolution along with high conversion rate, because each of the channels operates at a frequency that is lower by a factor of N than sampling frequency of the whole ADC, where N is the number of channels.
Theoretically, ADC channels characteristics (offset voltage, gain etc.) should be identical. However, mismatches such as offset and gain mismatches among channel ADCs as well as timing skew of the clocks distributed to them degrade accuracy parameters of the whole multichannel ADC. The main method to remove such distortion is calibration of each channel in multichannel ADC and thorough development of channels synchronization system [3].
This paper analyzes three channel mismatch effects in two-channel ADC:
offset mismatch;
gain mismatch;
timing skew of the clock.
THE INFLUENCE OF MAIN TYPES OF MISMATCH BETWEEN ADC CHANNELS AND THEIR INFLUENCE ON SPECTRUM
The Offset Mismatch Between ADC Channels
Let us suppose that offsets in ADC channels are different, while all the other parameters are identical. In this case each channel issues its own code error in output code of the whole ADC. Error repetition period for each channel equals N/fS, where N is ADC channels number and fS is ADC sampling frequency. In this case error signal may be presented in noise form, whose value does not depend on output signal amplitude and frequency.
Fig. 2 presents error signal in time domain. In frequency domain error signal of multichannel ADC manifests itself as a disturbance at frequencies k · fS/N, where fS is ADC sampling frequency, N is channels number, k = 1, 2, 3, … (for two-channel ADC see Fig. 7).
The Gain Mismatch Between ADC Channels
Let us suppose that gains in ADC channels are different, while other parameters are identical. In this case each channel issues its own code error in output code of the whole ADC. Error repetition period for each channel equals N/fS, where N is ADC channels number and fS is ADC sampling frequency. In this case, as opposed to the offset mismatch, error signal value will correlate with input signal amplitude causing the effect of error signal amplitude modulation by input signal. Hence, the largest error signal occurs at the peaks of input signal.
Fig. 3 presents error signal in time domain. In frequency domain error signal of multichannel ADC manifests itself as disturbance at frequencies ±fIN + k · fS/N, where fIN is input signal frequency, fS is ADC sampling frequency and N is channels number, k = 1, 2, 3, … (for two-channel ADC see Fig. 7).
The Timing Skew of the Clock in ADC Channels
Let us suppose that we have multichannel ADC with absolutely identical channels parameters, but with clock signals arrival with different delays (see Fig. 4). In this case each channel issues its own code error in output code of the whole ADC. Error repetition period for each channel equals N/fS, where N is ADC channels number and fS is ADC sampling frequency. In this case error signal value will correlate with the slew rate of input signal, so the largest error signal occurs when the input signal has the largest slew rate.
Fig. 5 presents error signal in time domain. In frequency domain error signal of multichannel ADC manifests itself as disturbance at frequencies ±fIN + k · fS/N, where fIN is input signal frequency, fS is ADC sampling frequency and N is channels number, k = 1, 2, 3, … (for two-channel ADC see Fig. 7).
It should be noted that in the offset and gain mismatch cases, the signal/noise ratio (S/N) at the output of multichannel ADC keeps constant as the input signal frequency increases, but in the timing skew case, S/N ratio at the output decreases as the input signal frequency increases (see Fig. 6).
Thus, being aware of influence of the mismatch effects between the channels of ADC on its output signal spectrum it is possible to make the following estimates:
to estimate dominating factors and degree of mismatch between channels before ADC calibration;
to estimate the quality of calibration of ADC parameters.
Due to difficulties caused by calibration of the clock skew, it is necessary to pay special attention to circuit and layout implementation of synchronization system and clock trees in multichannel ADCs.
REFERENCES
1. Waltari M. E., Halonen K. Circuits Techniques for Low-voltage and High-speed A/D Converters. // Kluwer Academic Publishers. 2002.
2. Sandeep Gupta, Michael Choi. A 1Gs/s 11b Time-interleaved ADC in 0.13mm CMOS // ISSCC 2006 / Session 31 / Very High-speed ADCs and DACs / 10.4.
3. Petraglia A. and Mitra S. K. “Analysis of Mismatch Effects Among A/D Converters in a Time-interleaved Waveform Digitizers”, IEEE Trans. Instrum. Meas., Vol. 40, pp. 831–835, Oct. 1991.
Modern electronics cannot do without high-performance analog-to-digital converters (ADC), because in signal processing systems ever more frequently direct signal processing at high frequencies is used without transferring signal spectrum to low frequencies region.
To decrease performance requirements for stages of high performance ADC, time-interleaved multichannel pipeline architecture has been used [1, 2], that is with partial overlapping of cycles of those channels that operate in parallel (see Fig. 1). Such architecture enables attaining high resolution along with high conversion rate, because each of the channels operates at a frequency that is lower by a factor of N than sampling frequency of the whole ADC, where N is the number of channels.
Theoretically, ADC channels characteristics (offset voltage, gain etc.) should be identical. However, mismatches such as offset and gain mismatches among channel ADCs as well as timing skew of the clocks distributed to them degrade accuracy parameters of the whole multichannel ADC. The main method to remove such distortion is calibration of each channel in multichannel ADC and thorough development of channels synchronization system [3].
This paper analyzes three channel mismatch effects in two-channel ADC:
offset mismatch;
gain mismatch;
timing skew of the clock.
THE INFLUENCE OF MAIN TYPES OF MISMATCH BETWEEN ADC CHANNELS AND THEIR INFLUENCE ON SPECTRUM
The Offset Mismatch Between ADC Channels
Let us suppose that offsets in ADC channels are different, while all the other parameters are identical. In this case each channel issues its own code error in output code of the whole ADC. Error repetition period for each channel equals N/fS, where N is ADC channels number and fS is ADC sampling frequency. In this case error signal may be presented in noise form, whose value does not depend on output signal amplitude and frequency.
Fig. 2 presents error signal in time domain. In frequency domain error signal of multichannel ADC manifests itself as a disturbance at frequencies k · fS/N, where fS is ADC sampling frequency, N is channels number, k = 1, 2, 3, … (for two-channel ADC see Fig. 7).
The Gain Mismatch Between ADC Channels
Let us suppose that gains in ADC channels are different, while other parameters are identical. In this case each channel issues its own code error in output code of the whole ADC. Error repetition period for each channel equals N/fS, where N is ADC channels number and fS is ADC sampling frequency. In this case, as opposed to the offset mismatch, error signal value will correlate with input signal amplitude causing the effect of error signal amplitude modulation by input signal. Hence, the largest error signal occurs at the peaks of input signal.
Fig. 3 presents error signal in time domain. In frequency domain error signal of multichannel ADC manifests itself as disturbance at frequencies ±fIN + k · fS/N, where fIN is input signal frequency, fS is ADC sampling frequency and N is channels number, k = 1, 2, 3, … (for two-channel ADC see Fig. 7).
The Timing Skew of the Clock in ADC Channels
Let us suppose that we have multichannel ADC with absolutely identical channels parameters, but with clock signals arrival with different delays (see Fig. 4). In this case each channel issues its own code error in output code of the whole ADC. Error repetition period for each channel equals N/fS, where N is ADC channels number and fS is ADC sampling frequency. In this case error signal value will correlate with the slew rate of input signal, so the largest error signal occurs when the input signal has the largest slew rate.
Fig. 5 presents error signal in time domain. In frequency domain error signal of multichannel ADC manifests itself as disturbance at frequencies ±fIN + k · fS/N, where fIN is input signal frequency, fS is ADC sampling frequency and N is channels number, k = 1, 2, 3, … (for two-channel ADC see Fig. 7).
It should be noted that in the offset and gain mismatch cases, the signal/noise ratio (S/N) at the output of multichannel ADC keeps constant as the input signal frequency increases, but in the timing skew case, S/N ratio at the output decreases as the input signal frequency increases (see Fig. 6).
Thus, being aware of influence of the mismatch effects between the channels of ADC on its output signal spectrum it is possible to make the following estimates:
to estimate dominating factors and degree of mismatch between channels before ADC calibration;
to estimate the quality of calibration of ADC parameters.
Due to difficulties caused by calibration of the clock skew, it is necessary to pay special attention to circuit and layout implementation of synchronization system and clock trees in multichannel ADCs.
REFERENCES
1. Waltari M. E., Halonen K. Circuits Techniques for Low-voltage and High-speed A/D Converters. // Kluwer Academic Publishers. 2002.
2. Sandeep Gupta, Michael Choi. A 1Gs/s 11b Time-interleaved ADC in 0.13mm CMOS // ISSCC 2006 / Session 31 / Very High-speed ADCs and DACs / 10.4.
3. Petraglia A. and Mitra S. K. “Analysis of Mismatch Effects Among A/D Converters in a Time-interleaved Waveform Digitizers”, IEEE Trans. Instrum. Meas., Vol. 40, pp. 831–835, Oct. 1991.
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