rus
Issue #9/2018
Chistyakov Mikhail G.
Research and Optimization by Radiation Hardness Criterion of Memory Cells for 0.25μm SOI CMOS Technology in the Course of Irradiation by Flux of Fast Neutrons
Research and Optimization by Radiation Hardness Criterion of Memory Cells for 0.25μm SOI CMOS Technology in the Course of Irradiation by Flux of Fast Neutrons
This paper presents the results of fault resistance researches performed for memory cells designed by 0.25µm SOI CMOS technology. Possible faults caused by hitting memory cell by fast neutrons are considered. The main approaches to memory cells hardening are also examined. Recommendations for memory cells hardening are provided.
Теги: memory cells resistance to charged particles impact soi sram кни созу стойкость к заряженным частицам ячейка памяти
Memory cell array (MC) is the most vulnerable to fault element in static random-access memory (SRAM) microcircuits when irradiated by fast neutrons. In the course of interaction between neutron and silicon primary knocked-on atoms are formed with energy attaining 960keV [1]. Linear energy transfer (LET) exhibited by silicon atoms reaches ~6МeV•mg/cm2 values. In case of SRAM microcircuits manufactured using SOI technology maximal impact is observed during silicon atom fly-over transistor’s body [2].
The faults number in the course of SRAM irradiation by fast neutrons depends on the amount of particles impacting on SRAM, with a characteristic threshold causing faults. Single faults caused by charged particles impact are described in detail in [2–4]. Since the indicated above works were focused on single particles impact, the present work investigates MC faults caused both by single particles and by two particles. In addition, memory cells were optimized by the criterion of resistance to the impact of particles in restricted energy spectrum (LET being not more than 7MeV • mg/cm2) at a minimal possible memory cell size increase. The selection of particles with 7МeV • mg/cm2 energy used for optimization is fully justified for providing guaranteed level of circuit stability and the device parameters margin in the course of its production. The area, time required for reading and writing operations within SRAM module as well as static noise margin (SNM) were estimated in the course of MC size optimization.
To perform the research we have selected six-transistor memory cell as most commonly used. Fig. 1 shows electrical diagram and memory cell topology. The original cell was designed in such a way as to occupy minimal area for achieving high density arrangement of memory cell array. The research was performed basing on MC electric circuit modelling using a model of electric perturbation caused by a charged particle impact [5].
The main modes of memory cell operation are data read, storage and write modes. Storage mode is most prolonged, if one considers each memory cell, and that is why a fault in storage mode is most probable.
The results of modelling indicate that the fault caused by a single particle impact is possible in the following kinds of impacts on memory cell (Fig. 2а, b):
• hitting n-channel transistor of memory cell inverter (Fig. 2а);
• hitting n-channel pass transistor of memory cell inverter (Fig. 2b));
The results of modelling show that the fault caused by the impact of two particles is possible in the following impacts on memory cell (Figs. 2c, d, e):
• simultaneously hitting p-channel transistor and n-channel transistor belonging to different MC inverters (Fig. 2c);
• simultaneously hitting n-channel MC pass-transistor and n-channel transistor of MC inverter (Fig. 2d);
• simultaneously hitting n-channel MC pass-transistor and n-channel transistor of MC inverter (Fig. 2e).
It should be noted that, according to the results of calculations, in case of a single particle impact (Fig. 2а, b) with LET equal to 7МeV•mg/cm2 no fault arises. It was found that a fault takes place at the impact of a particle with LET equal to 16МeV•mg/cm2. Fig. 3 presents the fault timing diagram in storage mode in case of impact with LET equal to 16МeV•mg/cm2 produced by a particle in transistor. In case of simultaneous impact produced by two particles (Figs. 2c, d,e) the fault is caused by a particle with LET equal to 7МeV•mg/cm2. Nevertheless, faults may arise at various values of particle LET. An example of fault caused by simultaneous impact produced by two particles is presented in Fig. 4.
Faults due to simultaneous impact produced by three particles have not been considered in this paper, because their probability is several orders of magnitude lower than in case of simultaneous impact of two
particles [3].
There are several approaches that can be used for reducing faults: an approach using redundant information and an approach based on electric diagram optimization in memory cells [6].
The approach using redundant information consists in correcting codes utilization, for example, Hamming code or majority voters requiring additional storage bits, as well as error-correcting schemes. Besides, an increase in digits per word, stored in memory, and in time of information storage results in double errors probability in the stored word. It should also be noted that in case of increasing logical elements number used for bits restoration, the usage rate of SRAM also increases.
The approach based on electric diagram optimization consists in the optimization of active elements size and in the addition of some passive elements into memory cells [4]. There exist other approaches towards fault protection, based, for example, on using memory cell DICE, but the area of such memory cell is approximately twice as large as the area of convenient 6-transistor MC, and for this reason is excessive for fault reflecting in case of impact produced by particles with restricted energy spectrum.
For attaining MC stability under the impact of silicon atom with LTE less than 7MeV•mg/cm2 and for minimizing the area occupied by MC the following passive elements were added:
1. Additional resistance in transistors circuit of MC inverters (Fig. 5).
2. Capacitor between feedback circuits of memory cell inverters (Fig. 6).
An additional resistor reduces the value of current impulse arising in transistors, and results in an increase in MC area approximately by 30 % if compared with the original memory cell. An additional capacitor smoothes current impulse and results in an increase in MC area approximately by 50 % if compared with the original memory cell.
It is also worth considering the use of two presented above modifications (Fig. 7).
In this case, an increase in memory cell size does not exceed 40 %.
The rating of passive elements was selected so as to attain resistance to impact of particles with LET equal to 7МeV•mg/cm2 and to provide minimal area. For comparison of all modifications we will use the following categories: area, operation speed, switching threshold and static noise margin (SNM).
Comparison of memory cells area is given in Table 1.
As can be seen in Table 1, memory cell with resistor occupies less area. Memory cell with resistor and capacitor has average area value. The highest area is occupied by memory cell with capacitor.
Time of read and write operations will be estimated within SRAM module with 1Кх32 architecture. Tables 2 and 3 contain the results of comparison of memory cells characteristics.
As is seen from Table 2, memory cell with resistor time to write “1” is 1 % less than required for original MC; as well as time for reading “1” and “0” does not differ from original MC. In case of memory cells with capacitor, time to write “1” and “0” is 9 % and 5 % greater than in case of original MC. Time to read “1” and “0” also does not differ. In case of memory cells with resistor and capacitor time for writing “1” and “0” increases by 4 % and 2 %, while time for reading does not alter. On the basis of comparison using time characteristics it is possible to single out memory cells with resistor, because their time parameters to write and to read are closest to the original memory cell.
For the purpose of analyzing the stability of writing operation, let us examine transfer characteristics of MC inverters. Using transfer characteristics, it is possible to determine MC switching threshold and SNM value. The switching threshold is defined as minimal voltage on internal MC node necessary for switching a cell into opposite state. SNM value is determined on the basis of transfer characteristics by maximum inscribed square and stands for maximum voltage value on internal node, at which MC does not flip into opposite state [6]. Transfer inverters characteristics of examined memory cells are presented on Fig. 8–11.
Table 4 contains values of switching threshold and SNM.
According to the obtained results of comparison (Table 4), memory cell with capacitor possesses the best characteristics, its values completely matching those of the original memory cell. Next goes memory cell with resistor and capacitor, which differs from original MC by 3 % in the switching threshold value and by 2 % in SNM value. The greatest difference from original MC is typical for memory cell with resistor: by 5 % in the switching threshold value and by 3 % in SNM value.
To summarize, we have researched the impact of charged particles with restricted energy spectrum (LET less than 7МeV•mg/cm2) on memory cell. A new method of memory cell research in case of simultaneous impact of two charged particles has been offered. Comparison of memory cells fault protection by means of different passive elements application has been conducted. For all investigated cases time to read and time to write, switching thresholds, as well as SNM values altered insignificantly (less than by 9 %). Memory cells with additional resistor provide the smallest difference in area as compared with original MC, and MC with capacitor occupies the largest area.
The proposed method can also be used for solving similar tasks with particles of another energy spectrum, as well as for analyzing neutrons impact.
REFERENCES
1. Stepovik A. P., Shukailo V. P., Shama-ev E. Yu. Effekt OS pri vozdeistvii neitronov s energiei 14MeV na KNI SBIS staticheskogo OZU: Tezisy dokladov Devyatogo mezhdunarodnogo ural'skogo seminara “Radiatsionnaya fizika metallov i splavov”, Kyshtym, 2011. P. 107–108. (In Russian).
2. James R. Schwank, Marty R. Shaneyfelt, and Paul E. Dodd: Radiation Hardness Assurance Testing of Microelectronic Devices and Integrated Circuits: Radiation Environments, Physical Mechanisms, and Foundations for Hardness Assurance, Sandia National Laboratories Document Sand, 2008 — 59 p.
3. Gorbunov M. S., Dolotov P. S., Anto¬nov A. A., Zebrev G. I., Emeliyanov V. V., Boruzdina A. B., Petrov A. G., Ulanova A. V.: Design of 65nm CMOS SRAM for Space Applications: a Comparative Study: Radiation and Its Effects on Components and Systems (RADECS), 2013 14th European Conference, IEEE, 2013. P. 1–7.
4. Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev. An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs: IEEE Transactions on Very Large Scale Iintegration (VLSI) Systems, Vol. 17, No. 9, September 2009 — pp. 1187–1195.
5. Del'tsov I. L., Morozov S. A., Chistyakov M. G., Sinepupova Yu. N. Metodika modelirovaniya urovnya stoikosti biblioteki standartnykh elementov k vozdeistviyu tyazheloi zaryazhennoi chastitsy dlya tekhnologii KNI 0,25mkm.: Sbornik dokladov Mezhdunarodnogo foruma “Mikroelektronika 2016” 2-i nauchnoi konferentsii “Integral'nye skhemy i mikroelektronnye moduli”, Respublika Krym, g. Alushta, 26–30 sentyabrya 2016, M., Izd-vo “Tekhnosfera”. P. 327–332. (In Russian).
6. Morozov S. A., Sokolov S. A.: Razrabotka radiatsionno-stoikikh mikroskhem i mikromodulei staticheskoi pamyati: Trudy NIISI RAN tom 4 № 1: Zhurnal — M.: NIISI RAN, 2014. P. 25–31. (In Russian).
The faults number in the course of SRAM irradiation by fast neutrons depends on the amount of particles impacting on SRAM, with a characteristic threshold causing faults. Single faults caused by charged particles impact are described in detail in [2–4]. Since the indicated above works were focused on single particles impact, the present work investigates MC faults caused both by single particles and by two particles. In addition, memory cells were optimized by the criterion of resistance to the impact of particles in restricted energy spectrum (LET being not more than 7MeV • mg/cm2) at a minimal possible memory cell size increase. The selection of particles with 7МeV • mg/cm2 energy used for optimization is fully justified for providing guaranteed level of circuit stability and the device parameters margin in the course of its production. The area, time required for reading and writing operations within SRAM module as well as static noise margin (SNM) were estimated in the course of MC size optimization.
To perform the research we have selected six-transistor memory cell as most commonly used. Fig. 1 shows electrical diagram and memory cell topology. The original cell was designed in such a way as to occupy minimal area for achieving high density arrangement of memory cell array. The research was performed basing on MC electric circuit modelling using a model of electric perturbation caused by a charged particle impact [5].
The main modes of memory cell operation are data read, storage and write modes. Storage mode is most prolonged, if one considers each memory cell, and that is why a fault in storage mode is most probable.
The results of modelling indicate that the fault caused by a single particle impact is possible in the following kinds of impacts on memory cell (Fig. 2а, b):
• hitting n-channel transistor of memory cell inverter (Fig. 2а);
• hitting n-channel pass transistor of memory cell inverter (Fig. 2b));
The results of modelling show that the fault caused by the impact of two particles is possible in the following impacts on memory cell (Figs. 2c, d, e):
• simultaneously hitting p-channel transistor and n-channel transistor belonging to different MC inverters (Fig. 2c);
• simultaneously hitting n-channel MC pass-transistor and n-channel transistor of MC inverter (Fig. 2d);
• simultaneously hitting n-channel MC pass-transistor and n-channel transistor of MC inverter (Fig. 2e).
It should be noted that, according to the results of calculations, in case of a single particle impact (Fig. 2а, b) with LET equal to 7МeV•mg/cm2 no fault arises. It was found that a fault takes place at the impact of a particle with LET equal to 16МeV•mg/cm2. Fig. 3 presents the fault timing diagram in storage mode in case of impact with LET equal to 16МeV•mg/cm2 produced by a particle in transistor. In case of simultaneous impact produced by two particles (Figs. 2c, d,e) the fault is caused by a particle with LET equal to 7МeV•mg/cm2. Nevertheless, faults may arise at various values of particle LET. An example of fault caused by simultaneous impact produced by two particles is presented in Fig. 4.
Faults due to simultaneous impact produced by three particles have not been considered in this paper, because their probability is several orders of magnitude lower than in case of simultaneous impact of two
particles [3].
There are several approaches that can be used for reducing faults: an approach using redundant information and an approach based on electric diagram optimization in memory cells [6].
The approach using redundant information consists in correcting codes utilization, for example, Hamming code or majority voters requiring additional storage bits, as well as error-correcting schemes. Besides, an increase in digits per word, stored in memory, and in time of information storage results in double errors probability in the stored word. It should also be noted that in case of increasing logical elements number used for bits restoration, the usage rate of SRAM also increases.
The approach based on electric diagram optimization consists in the optimization of active elements size and in the addition of some passive elements into memory cells [4]. There exist other approaches towards fault protection, based, for example, on using memory cell DICE, but the area of such memory cell is approximately twice as large as the area of convenient 6-transistor MC, and for this reason is excessive for fault reflecting in case of impact produced by particles with restricted energy spectrum.
For attaining MC stability under the impact of silicon atom with LTE less than 7MeV•mg/cm2 and for minimizing the area occupied by MC the following passive elements were added:
1. Additional resistance in transistors circuit of MC inverters (Fig. 5).
2. Capacitor between feedback circuits of memory cell inverters (Fig. 6).
An additional resistor reduces the value of current impulse arising in transistors, and results in an increase in MC area approximately by 30 % if compared with the original memory cell. An additional capacitor smoothes current impulse and results in an increase in MC area approximately by 50 % if compared with the original memory cell.
It is also worth considering the use of two presented above modifications (Fig. 7).
In this case, an increase in memory cell size does not exceed 40 %.
The rating of passive elements was selected so as to attain resistance to impact of particles with LET equal to 7МeV•mg/cm2 and to provide minimal area. For comparison of all modifications we will use the following categories: area, operation speed, switching threshold and static noise margin (SNM).
Comparison of memory cells area is given in Table 1.
As can be seen in Table 1, memory cell with resistor occupies less area. Memory cell with resistor and capacitor has average area value. The highest area is occupied by memory cell with capacitor.
Time of read and write operations will be estimated within SRAM module with 1Кх32 architecture. Tables 2 and 3 contain the results of comparison of memory cells characteristics.
As is seen from Table 2, memory cell with resistor time to write “1” is 1 % less than required for original MC; as well as time for reading “1” and “0” does not differ from original MC. In case of memory cells with capacitor, time to write “1” and “0” is 9 % and 5 % greater than in case of original MC. Time to read “1” and “0” also does not differ. In case of memory cells with resistor and capacitor time for writing “1” and “0” increases by 4 % and 2 %, while time for reading does not alter. On the basis of comparison using time characteristics it is possible to single out memory cells with resistor, because their time parameters to write and to read are closest to the original memory cell.
For the purpose of analyzing the stability of writing operation, let us examine transfer characteristics of MC inverters. Using transfer characteristics, it is possible to determine MC switching threshold and SNM value. The switching threshold is defined as minimal voltage on internal MC node necessary for switching a cell into opposite state. SNM value is determined on the basis of transfer characteristics by maximum inscribed square and stands for maximum voltage value on internal node, at which MC does not flip into opposite state [6]. Transfer inverters characteristics of examined memory cells are presented on Fig. 8–11.
Table 4 contains values of switching threshold and SNM.
According to the obtained results of comparison (Table 4), memory cell with capacitor possesses the best characteristics, its values completely matching those of the original memory cell. Next goes memory cell with resistor and capacitor, which differs from original MC by 3 % in the switching threshold value and by 2 % in SNM value. The greatest difference from original MC is typical for memory cell with resistor: by 5 % in the switching threshold value and by 3 % in SNM value.
To summarize, we have researched the impact of charged particles with restricted energy spectrum (LET less than 7МeV•mg/cm2) on memory cell. A new method of memory cell research in case of simultaneous impact of two charged particles has been offered. Comparison of memory cells fault protection by means of different passive elements application has been conducted. For all investigated cases time to read and time to write, switching thresholds, as well as SNM values altered insignificantly (less than by 9 %). Memory cells with additional resistor provide the smallest difference in area as compared with original MC, and MC with capacitor occupies the largest area.
The proposed method can also be used for solving similar tasks with particles of another energy spectrum, as well as for analyzing neutrons impact.
REFERENCES
1. Stepovik A. P., Shukailo V. P., Shama-ev E. Yu. Effekt OS pri vozdeistvii neitronov s energiei 14MeV na KNI SBIS staticheskogo OZU: Tezisy dokladov Devyatogo mezhdunarodnogo ural'skogo seminara “Radiatsionnaya fizika metallov i splavov”, Kyshtym, 2011. P. 107–108. (In Russian).
2. James R. Schwank, Marty R. Shaneyfelt, and Paul E. Dodd: Radiation Hardness Assurance Testing of Microelectronic Devices and Integrated Circuits: Radiation Environments, Physical Mechanisms, and Foundations for Hardness Assurance, Sandia National Laboratories Document Sand, 2008 — 59 p.
3. Gorbunov M. S., Dolotov P. S., Anto¬nov A. A., Zebrev G. I., Emeliyanov V. V., Boruzdina A. B., Petrov A. G., Ulanova A. V.: Design of 65nm CMOS SRAM for Space Applications: a Comparative Study: Radiation and Its Effects on Components and Systems (RADECS), 2013 14th European Conference, IEEE, 2013. P. 1–7.
4. Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev. An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs: IEEE Transactions on Very Large Scale Iintegration (VLSI) Systems, Vol. 17, No. 9, September 2009 — pp. 1187–1195.
5. Del'tsov I. L., Morozov S. A., Chistyakov M. G., Sinepupova Yu. N. Metodika modelirovaniya urovnya stoikosti biblioteki standartnykh elementov k vozdeistviyu tyazheloi zaryazhennoi chastitsy dlya tekhnologii KNI 0,25mkm.: Sbornik dokladov Mezhdunarodnogo foruma “Mikroelektronika 2016” 2-i nauchnoi konferentsii “Integral'nye skhemy i mikroelektronnye moduli”, Respublika Krym, g. Alushta, 26–30 sentyabrya 2016, M., Izd-vo “Tekhnosfera”. P. 327–332. (In Russian).
6. Morozov S. A., Sokolov S. A.: Razrabotka radiatsionno-stoikikh mikroskhem i mikromodulei staticheskoi pamyati: Trudy NIISI RAN tom 4 № 1: Zhurnal — M.: NIISI RAN, 2014. P. 25–31. (In Russian).
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