rus
Issue #9/2018
Fateyev Ivan A., Shalashova Elena S.
Developing a Trigger Set With Enhanced Mitigation to Heavy Charged Particles Impact on the Base of SOI CMOS Technology
Developing a Trigger Set With Enhanced Mitigation to Heavy Charged Particles Impact on the Base of SOI CMOS Technology
Modern microcircuits due to technological features size scaling, decrease of voltage supply and internal capacities, are becoming ever more sensitive to heavy particles impact. Conventional process-dedicated cells, resistant to heavy particles impact, lose their advantages because of heavy particles impact on a number of sensitive areas. This paper presents a radiation-hardened set of D-triggers with and without reset and set-up signals developed on the base of DICE element using 200nm SOI technology.
Теги: dice fault tolerance heavy charged particle radiation resistance see seu single faults soi кни одиночные сбои радиационная стойкость сбоеустойчивость тзч
Space on-board instrumentation in the course of its service life is subjected to the impact of different factors, which cause faults and damages to on-board instrumentation components. That is why to ensure long service life of on-board instrumentation it is important to provide its resistance to the impact of ionizing radiation (IR). The main sources of ionizing radiation in space are solar cosmic rays (SCR), galactic cosmic rays (GCR) and natural Earth radiation belts (NERB) (Table 1) [1,2].
The impact of space radiation may cause undesirable effects in semiconductor devices, which can be conventionally classified into local or single and doze effect groups. As minimal element size decreases, doze effects also tend to be less. As the degree of integration increases, Single Event Effects (SEE) are becoming prevalent [3, 4].
Single event effects appear when an occasional heavy charged particle hits the semiconductor, and are characterized by probability of occurrence. Heavy charged particles (HCP) leave after their passage an ionized track, whose diameter increases along with the particle energy. The sensitive area in IC is reverse-biased p-n junction [2]. Electron-hole pairs, released by a flying-over ion, result in the appearance of current and voltage impulse, which may cause electronics faults or failures.
SEE may be divided into two groups: reversible and irreversible effects. The second group is more dangerous, because its effects result in destructive consequences. This group includes: single event latchups (SEL), single-event gate rupture (SEGR) and others. The following types of reversible failures are singled out: data inversion in memory cells without performance loss (Single Event Upset, SEU), change of logical state of a node in combinatorial logic, which further propagates circuit-wise (Single Event Transient, SET), Single Event Functional Interrupt (SEFI) [1, 3, 4]. A considerable part of functional failures is conditioned by single events effects in control registers and in memory, while a considerable part of functional failures is conditioned by SEL in CMOS integrated circuits. Thus, SEU and SET are the most critical local effects for modern integrated circuits (IC) with a high degree of integration.
As a rule, VLSI tolerance enhancement by means of design methods is conducted with process-dedicated memory cells and hardened to single nucleons impact triggers (DICE, NASA, TMR and their modifications) [5]. In this work preference has been given to triggers on DICE-cell base (Dual Interlocked Cell) [2]. In effect, DICE structure (Fig. 1) is a memory cell, which uses data redundancy. So, if any particle strikes sensitive node 0 or 1, then a special circuit of transistors connection prevents failure propagation to the second data copy (2 or 3), and some time after the affected node restores (by means of feedbacks) its original state.
The technology development has made it possible to decrease minimal element size and, as a result, to reduce the distance between microcircuit elements. The effective diameter of heavy charged particle track is a micron by order of magnitude, and at proton energy of 1GeV the track diameter exceeds 0.9 micron [6]. Closely placed sensitive areas increase the probability of impact by heavy charged particle fluttering down at low angle simultaneously to a number of nodes, thus reducing the efficiency of DICE architecture application. Considering the above mentioned, it is possible to conclude that an increase in distance between sensitive transistor drains enhances tolerance to single events upset induced by heavy charged particles, because the data will be stored simultaneously in both nodes spaced far enough from each other, and it will help to prevent change in the cell state [7, 8].
To provide immunity from single event effects (SEE) DICE-cell has been used and on its base a set of D-triggers with and without asynchronous set-up and reset signals have been developed, using 200nm SOI-technology. To prevent the transient process propagation, the trigger output is provided with C-element, which changes output value in case of identical signals at inputs. In case of differential signals it proceeds into Z and in load capacitance the previous state is stored [8]. Fig. 2 presents the trigger circuit with reset signal RN and output Q.
Upon analysis of the circuit presented on Fig. 1, the following sets of sensitive nodes have been singled out: in case of Q = 1, drains of transistors N0, N2, P1, P3, RN are sensitive areas, whose relative position should be considered at the stage of layout design; in case of Q = 0, drains of transistors N1, N3, P0, P2 will be sensitive areas of the circuit.
Fig. 3 presents topology of D-trigger circuit with asynchronous reset signal RN, with indicated spaces between sensitive pairs of p-n junctions being reverse biased in one of the logic states. For efficient area utilization and provision of maximum achievable spaces between sensitive sets, transistors from two latches have been mixed, without artificially increasing the area.
Fig. 4 presents D-trigger circuit with set signal SN. Sensitive areas are provided with additional drains of transistors with SN signal. Topology is presented on Fig. 5.
Tables 2 and 3 contain spaces between drains of transistors being reversely biased, which may result in failure caused by simultaneous impact of heavy charged particles. So, an increase in the distance between sensitive areas of transistors results in a decrease in impact sector in isotropic space, thus reducing the probability of data inversion in DICE latch. The use of С-element at the output hinders SET propagation along loaded circuit.
Within the frame of the current work, layouts of trigger without reset and set signals have been designed, as well as trigger, whose topology does not provide for mixing two different latches and, respectively, there is no increase in spaces between sensitive areas. The comparison of areas occupied by triggers presented in Table 4 demonstrates that the area occupied by trigger without additional signals is 8 % less than the one occupied by trigger with reset or set signal, but distance between critical nodes also reduces in this case. If transistors sensitive drains are spaced far enough, the area increases by 5 % compared to the same trigger without applying this method.
CONCLUSIONS
This work presents a set of D-triggers with asynchronous set and reset signals and without these signals developed on the base of DICE architecture with unique circuit implementation. Respective topology has been developed by means of 200nm SOI technology. The sensitive trigger nodes analysis has been carried out. A set of transistors whose relative allocation affects trigger resistance to heavy charged particles impact has been singled out, and requires special attention.
The report highlights the layout of the above mentioned variants of trigger circuit developed using Cadence CAD. Stray parameters have been extracted by means of Mentor Graphics Calibre product. Basing on these data, the rise time, fall time and delay time have been calculated (Table 4).
While creating the layout, relative allocation of sensitive nodes has been considered. For efficient area utilization and provision of maximum achievable spaces between sensitive sets, transistors from two latches were mixed, without artificially increasing the area. Minimal distance between sensitive nodes turned to be 7.331 microns, while using ordinary allocation this distance makes 1.55 microns. The presented D-trigger modification increases area by 5 %, but may also increase resistance to SEU.
REFERENCES
1. Chumakov A. I. Deistvie kosmicheskoi radiatsii na integral'nye skhemy. M.: Radio i svyaz', 2004. 320 p. (In Russian).
2. Tapero K. I., Ulimov V. N., Chlenov A. M. Radiatsionnye effekty v kremnievykh integral'nykh skhemakh kosmicheskogo primeneniya. M.: Binom, 2012. 306 p. (In Russian).
3. Calin T., Nicolaidis M., and Velazco R. Upset Hardened Memory Design for Submicron CMOS Technology // Nuclear Science, IEEE Transactions on — 1996, Vol. 43, Issue 6, Part 1, pp. 2874–2878.
4. Zebrev G. I. Radiatsionnye effekty v kremnievykh integral'nykh skhemakh vysokoi stepeni integratsii. M.: NIYaU MIFI, 2010. — P. 148. (In Russian).
5. Dolotov P. S. Ustoichivye k vozdeistviyu tyazhelykh zaryazhennykh chastits KMOP bloki staticheskogo OZU na osnove tekhnologii ob"emnogo kremniya i «kremnii na izolyatore»: dis. kand. tekhn. nauk: 05.13.05/Dolotov Pavel Sergeevich. Moskva, 2015. 183 p. (In Russian).
6. Ol'chev S. I., Stenin V. Ya. Analiz sboeustoichivosti triggernykh elementov s dvukhfaznoi strukturoi // Elektronika, mikro- i nanoelektronika. Sb. nauchn. trudov. M.: NIYaU MIFI, 2010. P. 29–38. (In Russian).
7. Stenin V. Ya., Cherkasov I. G. Vliyanie topologii submikronnykh KMOP yacheek pamyati DICE na chuvstvitel'nost' OZU k vozdeistviyu otdel'nykh yadernykh chastits // Mikroelektronika. 2011. Vol. 40. № 3. P. 184–190. (In Russian).
8. Stenin V. Ya., Stepanov P. V. Proektirovanie bazovykh elementov pamyati na osnove yacheek DICE dlya sboeustoichivykh KMOP 28nm OZU // MES-2014. (In Russian).
9. Mitra S., Zhang M., Waqas S., Seifert N., Gill B., and Kim K. Combinational Logic Soft Error Correction // in Proc. IEEE International Test Conf. on — 2006, pp. 824–832.
10. Lilja K., Bounasser M., Wen S., Wong R., Holst J., Gaspard N., Jagannathan S., Loveless D., Bhuva B. Single-event Performance and Layout Optimization of Flip-flops in a 28-nm Bulk Technology // IEEE Transactions on Nuclear Science — 2013, Vol. 60. № 4, pp. 2782–2788
The impact of space radiation may cause undesirable effects in semiconductor devices, which can be conventionally classified into local or single and doze effect groups. As minimal element size decreases, doze effects also tend to be less. As the degree of integration increases, Single Event Effects (SEE) are becoming prevalent [3, 4].
Single event effects appear when an occasional heavy charged particle hits the semiconductor, and are characterized by probability of occurrence. Heavy charged particles (HCP) leave after their passage an ionized track, whose diameter increases along with the particle energy. The sensitive area in IC is reverse-biased p-n junction [2]. Electron-hole pairs, released by a flying-over ion, result in the appearance of current and voltage impulse, which may cause electronics faults or failures.
SEE may be divided into two groups: reversible and irreversible effects. The second group is more dangerous, because its effects result in destructive consequences. This group includes: single event latchups (SEL), single-event gate rupture (SEGR) and others. The following types of reversible failures are singled out: data inversion in memory cells without performance loss (Single Event Upset, SEU), change of logical state of a node in combinatorial logic, which further propagates circuit-wise (Single Event Transient, SET), Single Event Functional Interrupt (SEFI) [1, 3, 4]. A considerable part of functional failures is conditioned by single events effects in control registers and in memory, while a considerable part of functional failures is conditioned by SEL in CMOS integrated circuits. Thus, SEU and SET are the most critical local effects for modern integrated circuits (IC) with a high degree of integration.
As a rule, VLSI tolerance enhancement by means of design methods is conducted with process-dedicated memory cells and hardened to single nucleons impact triggers (DICE, NASA, TMR and their modifications) [5]. In this work preference has been given to triggers on DICE-cell base (Dual Interlocked Cell) [2]. In effect, DICE structure (Fig. 1) is a memory cell, which uses data redundancy. So, if any particle strikes sensitive node 0 or 1, then a special circuit of transistors connection prevents failure propagation to the second data copy (2 or 3), and some time after the affected node restores (by means of feedbacks) its original state.
The technology development has made it possible to decrease minimal element size and, as a result, to reduce the distance between microcircuit elements. The effective diameter of heavy charged particle track is a micron by order of magnitude, and at proton energy of 1GeV the track diameter exceeds 0.9 micron [6]. Closely placed sensitive areas increase the probability of impact by heavy charged particle fluttering down at low angle simultaneously to a number of nodes, thus reducing the efficiency of DICE architecture application. Considering the above mentioned, it is possible to conclude that an increase in distance between sensitive transistor drains enhances tolerance to single events upset induced by heavy charged particles, because the data will be stored simultaneously in both nodes spaced far enough from each other, and it will help to prevent change in the cell state [7, 8].
To provide immunity from single event effects (SEE) DICE-cell has been used and on its base a set of D-triggers with and without asynchronous set-up and reset signals have been developed, using 200nm SOI-technology. To prevent the transient process propagation, the trigger output is provided with C-element, which changes output value in case of identical signals at inputs. In case of differential signals it proceeds into Z and in load capacitance the previous state is stored [8]. Fig. 2 presents the trigger circuit with reset signal RN and output Q.
Upon analysis of the circuit presented on Fig. 1, the following sets of sensitive nodes have been singled out: in case of Q = 1, drains of transistors N0, N2, P1, P3, RN are sensitive areas, whose relative position should be considered at the stage of layout design; in case of Q = 0, drains of transistors N1, N3, P0, P2 will be sensitive areas of the circuit.
Fig. 3 presents topology of D-trigger circuit with asynchronous reset signal RN, with indicated spaces between sensitive pairs of p-n junctions being reverse biased in one of the logic states. For efficient area utilization and provision of maximum achievable spaces between sensitive sets, transistors from two latches have been mixed, without artificially increasing the area.
Fig. 4 presents D-trigger circuit with set signal SN. Sensitive areas are provided with additional drains of transistors with SN signal. Topology is presented on Fig. 5.
Tables 2 and 3 contain spaces between drains of transistors being reversely biased, which may result in failure caused by simultaneous impact of heavy charged particles. So, an increase in the distance between sensitive areas of transistors results in a decrease in impact sector in isotropic space, thus reducing the probability of data inversion in DICE latch. The use of С-element at the output hinders SET propagation along loaded circuit.
Within the frame of the current work, layouts of trigger without reset and set signals have been designed, as well as trigger, whose topology does not provide for mixing two different latches and, respectively, there is no increase in spaces between sensitive areas. The comparison of areas occupied by triggers presented in Table 4 demonstrates that the area occupied by trigger without additional signals is 8 % less than the one occupied by trigger with reset or set signal, but distance between critical nodes also reduces in this case. If transistors sensitive drains are spaced far enough, the area increases by 5 % compared to the same trigger without applying this method.
CONCLUSIONS
This work presents a set of D-triggers with asynchronous set and reset signals and without these signals developed on the base of DICE architecture with unique circuit implementation. Respective topology has been developed by means of 200nm SOI technology. The sensitive trigger nodes analysis has been carried out. A set of transistors whose relative allocation affects trigger resistance to heavy charged particles impact has been singled out, and requires special attention.
The report highlights the layout of the above mentioned variants of trigger circuit developed using Cadence CAD. Stray parameters have been extracted by means of Mentor Graphics Calibre product. Basing on these data, the rise time, fall time and delay time have been calculated (Table 4).
While creating the layout, relative allocation of sensitive nodes has been considered. For efficient area utilization and provision of maximum achievable spaces between sensitive sets, transistors from two latches were mixed, without artificially increasing the area. Minimal distance between sensitive nodes turned to be 7.331 microns, while using ordinary allocation this distance makes 1.55 microns. The presented D-trigger modification increases area by 5 %, but may also increase resistance to SEU.
REFERENCES
1. Chumakov A. I. Deistvie kosmicheskoi radiatsii na integral'nye skhemy. M.: Radio i svyaz', 2004. 320 p. (In Russian).
2. Tapero K. I., Ulimov V. N., Chlenov A. M. Radiatsionnye effekty v kremnievykh integral'nykh skhemakh kosmicheskogo primeneniya. M.: Binom, 2012. 306 p. (In Russian).
3. Calin T., Nicolaidis M., and Velazco R. Upset Hardened Memory Design for Submicron CMOS Technology // Nuclear Science, IEEE Transactions on — 1996, Vol. 43, Issue 6, Part 1, pp. 2874–2878.
4. Zebrev G. I. Radiatsionnye effekty v kremnievykh integral'nykh skhemakh vysokoi stepeni integratsii. M.: NIYaU MIFI, 2010. — P. 148. (In Russian).
5. Dolotov P. S. Ustoichivye k vozdeistviyu tyazhelykh zaryazhennykh chastits KMOP bloki staticheskogo OZU na osnove tekhnologii ob"emnogo kremniya i «kremnii na izolyatore»: dis. kand. tekhn. nauk: 05.13.05/Dolotov Pavel Sergeevich. Moskva, 2015. 183 p. (In Russian).
6. Ol'chev S. I., Stenin V. Ya. Analiz sboeustoichivosti triggernykh elementov s dvukhfaznoi strukturoi // Elektronika, mikro- i nanoelektronika. Sb. nauchn. trudov. M.: NIYaU MIFI, 2010. P. 29–38. (In Russian).
7. Stenin V. Ya., Cherkasov I. G. Vliyanie topologii submikronnykh KMOP yacheek pamyati DICE na chuvstvitel'nost' OZU k vozdeistviyu otdel'nykh yadernykh chastits // Mikroelektronika. 2011. Vol. 40. № 3. P. 184–190. (In Russian).
8. Stenin V. Ya., Stepanov P. V. Proektirovanie bazovykh elementov pamyati na osnove yacheek DICE dlya sboeustoichivykh KMOP 28nm OZU // MES-2014. (In Russian).
9. Mitra S., Zhang M., Waqas S., Seifert N., Gill B., and Kim K. Combinational Logic Soft Error Correction // in Proc. IEEE International Test Conf. on — 2006, pp. 824–832.
10. Lilja K., Bounasser M., Wen S., Wong R., Holst J., Gaspard N., Jagannathan S., Loveless D., Bhuva B. Single-event Performance and Layout Optimization of Flip-flops in a 28-nm Bulk Technology // IEEE Transactions on Nuclear Science — 2013, Vol. 60. № 4, pp. 2782–2788
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