rus
Issue #9/2018
Fateyev Ivan A., Shalashova Elena S
The Infl uence of Clock Gating Cells on Navigation Receiver Path Immunity to Single Nuclear Particles Impact
The Infl uence of Clock Gating Cells on Navigation Receiver Path Immunity to Single Nuclear Particles Impact
In this article described the effect of clock gating cell on heavy ion hit vulnerability. The schemes with and without clock gating cells are compared. Shown the influence of clock gating cell presence on the susceptible areas.
INTRODUCTION
Space vehicles during their active service life in cosmic space are exposed to the impact of various factors. Fluxes of high energy elementary particles are one of the main factors affecting reliable functioning of microcircuits, constituting a part of air-borne equipment.
The impact of heavy charged particles on VLSIs results in various upsets of their operation and even may lead to catastrophic failures. In the course of the particle passage through semiconductor’s material a heavy charged particle track is left with the footprint located on semiconductor’s surface; the larger is the footprint diameter, the higher is the particle energy [1–3]. The activated electron-hole pairs with charge Q initiate current and voltage impulse at one of the contacts. The margin of upset resistance is characterized by Qcrit or critical charge required for triggering the storage element and for causing upset. If collected charge caused by heavy charged particle impact is less than critical one (Q < Qcrit), temporary signal level disturbance occurs at storage elements output without their subsequent state change.
An increase in performance is attributed to a decrease in minimum feature size, which in its turn results in the reductions of voltage supply, internal capacities, critical charge and an increase in vulnerability to single nuclear particles impact. At the same time, the effect of total accumulated doze decreases with reduction of oxides thickness. That is why predominance of single events effect (SEE) over ionization doze (TID) is typical for modern CMOS microcircuits [4].
SINGLE EVENTS MITIGATION
Currently there is a large number of investigations devoted to developing new variants of upset resistant cells, such as DICE, NASA, HIT, Hiper [6–9]. Increase in upset resistance in these cells is attained by additional data copies and internal feedbacks used for state restoring. With application of special-purpose cells, vulnerability to SEU of CMOS circuit reduces. In this case single event transient (SET) contribution in upset rate increases.
Single event transient appears in the form of short voltage pulse at combination logic input under heavy charged particle impact. With further propagation through the circuit this pulse may be written into memory cell distorting stored data. Circuit susceptibility to SET strongly depends on the operating frequency and size of “vulnerability window”, time segment near active share plane of clock signal [8].
Special attention should be paid to clock tree elements. In case of SET appearance at clock input, anomalous data may be written inside triggers. This research analyses how the clock gating cell affects memory registers upset resistance. Clock gating cells implementation is a part of standard design route and may be performed automatically, using special options of logical synthesis software (Fig. 1). The principle of clock gating cell operation consists in the following: in the presence of enabling signal at the input (EN = “1”) the clock signal passes through the cell at triggers register, in the presence of disabling signal the clock signal is interlocked.
PROBABILITY OF FAULTLESS OPERATION WITH CLOCK GATING CELL AND WITHOUT IT
As the probability of faultless system operation is equal to the product of faultless operation probabilities of its parts [10], it is possible to compute probability of faultless circuit operation Pwocg without clock gating cell as presented on Fig. 2:
where QD is probability of single event at trigger, QEN — probability of single event on EN node, QMUX — probability of single event at multiplexer, QBUF — probability of single event at clock tree buffer, QCLK — probability of single event at clock tree, N — register word length, К — amount of clock buffers.
Probability of faultless circuit operation with clock gating cell presented on Fig. 3 can be computed similarly:
where QD is probability of single event at trigger, QEN — probability of single event on EN node, QBUF — probability of single event at clock tree buffer, QCLK — probability of single event at clock tree, QCG — probability of single event at clock tree, N — register word length, К — amount of clock buffers.
Let us assume the following:
• Probabilities of single events for all triggers are identical;
• Window of vulnerability (WoV) is the same.
These assumptions may be done proceeding from the fact that while designing complex digital systems libraries of standard cell are applied. Therefore, triggers will have identical layout and, correspondingly, identical characteristics in terms of critical charge and internal nodes capacities.
Consequently, it is possible to express the ratio of faultless operation probabilities with clock gating cell and without it by the following formula:
.(1)
From (1) one can see that the ratio of faultless operation probabilities for circuits with clock gating cell and without it reduces to a probability of SET arising at multiplexor or at clock gating cell.
METHODS OF CALCULATING SET ARISING PROBABILITY
First, it is necessary to examine the probability of SET arising for NAND-cell presented on Fig. 4.
Probability of SET arising at NAND-cell input may be divided into two constituents. SET may arise as a result of impact on internal transistors QINT or as a result of external impacts on input nodes QEXT.
Probability of SET arising for internal transistors depends on actual condition of input signals. For combinations at AB input equalling “00”, output equals “1”; then in case of heavy charged particle impact on reversely biased p-n junction of 2nd transistor, transient process from “1” to “0” may arise. In a similar way it is possible to determine probability for each combination of input data. Assuming the duty ratio of input signals being equal to ¼ in any possible state, we can compute:
(2)
where Q0, Q1, Q2, Q3 are probabilities of SET arising at transistors presented on Fig. 4.
Probability of SET arising at external inputs also depends on the state and can be computed by the following formula:
(3)
where QAR, QBR are probabilities of negative SET arising, QBF, QAF — probabilities of positive SET arising at inputs, resulting in change of output voltage.
Let us introduce two new indices, QNANDR and QNANDF. QNANDR are probabilities of negative SET arising in case of output value “1”. QNANDF is probability of positive SET arising in case of output value “0”. These indices can be calculated using formulas (4) and (5):
(4)
(5)
where QINTF and QINTR are probabilities of positive and negative pulse of transient process, caused by heavy charged particle impact on “closed” transistors of NAND cell.
This method can be used for estimating probability of SET arising in inverter cell presented on Fig. 5.
Probability of SET arising at inverter input may be estimated using formulas (6) and (7):
(6)
where QAF is probability of positive SET arising at inverter input А and Q4 — probability of SET arising in “closed” 4th transistor.
(7)
where QAR is probability of negative SET arising at inverter input А and Q5 — probability of SET arising in “closed” 5th transistor.
ESTIMATING PROBABILITY OF SET ARISING AT CLOCK GATING CELL AND AT MULTIPLEXOR
Let us take a look at the structure of presented on Fig. 6 multiplexor.
Using formulas (4)–(7) it is possible to calculate probabilities of SET arising for all internal nodes. So, for N node we obtain:
(8)
(9)
where QKR, QKF, QLR, QLF — are probabilities of SET arising for nodes K and L respectively.
Adding the results of (8) and (9) we will obtain probability of SET arising for node N, that is QMUX.
Let us examine the next structure of clock gating cell presented on Fig. 7.
Taking in consideration that “latch” consists of two cells of inverter, it is possible to estimate the probability of positive and negative SET arising for P node:
(10)
(11)
where QENF and QENR are probabilities of negative and positive voltage pulse arising at EN input, t — “window of vulnerability” (WoV) size, T — clock cycle.
Using expressions (12) and (13) we can calculate the probability of SET arising for R node, that is QMUX.
(12)
(13)
Fig. 8 presents a diagram of QN and QR depending on SET arising probability at internal nodes. On this figure one can see that QN surpasses QR.
Fig. 9 presents a diagram of Pcg/Pwocg ratio depending on probability of SET arising at internal nodes in logarithmic scale for 32 and 8 triggers in register. On this diagram one can see that probability of circuit faultless operation with clock gating cell is higher than without it. Besides, with an increase in register capacity, the advantage of variant with clock gating cell is growing.
Let us calculate in a similar way faultless circuit operation probabilities with and without clock gating cell for standard “latches”, for latches of DICE-type, variants with sparse signal EN. It should be noted that in case of sparse EN the following assumption was made: EN very seldom transits from “0” into “1”, which means that QENF tends to 0. This variant of operation is typical for configuration registers in reception paths, in which data variations occur once in several millions of clocks [11].
Fig. 10 presents a diagram of faultless circuit operation probability with clock gating cell and standard “latch” (STD and STDLR — sparse signal EN), with clock gating cell and DICE “latch” (DICE and DICELR) and without clock gating cell (MUX and MUXLR).
RESULTS
The research has resulted in a method making it possible to conduct qualitative comparison of combinational circuits. It has been found that the application of clock gating cells enables one to increase faultless operation probability for registers of arbitrary word length, while an increase in word length leads to an increase in relative probability of faultless operation for circuits with clock gating cell. The calculations have shown that to increase faultless operation probability clock gating cells have to be automatically installed on registers whose capacity is no less than 1, instead of capacity 3 in accordance with low power ideology. The application of a “latch” of DICE type in clock gating cell will make it possible not only to reduce the probability of SEU arising in the cell, but also to reduce the probability of SEU arising in the whole circuit.
REFERENCES
1. Chumakov A. I. Deistvie kosmicheskoi radiatsii na integral'nye skhemy. M.: Radio i svyaz', 2004. 320 p. (In Russian).
2. Tapero K. I., Ulimov V. N., Chlenov A. M. Radiatsionnye effekty v kremnievykh integral'nykh skhemakh kosmicheskogo primeneniya. M.: BINOM. Laboratoriya znanii, 2012. 304 p. (In Russian).
3. Ionizing Radiation Effects in MOS Devices and Circuits / Ed. by T.-P. Ma and P. V. Dressendorfer. — N.-Y.: Wiley, 1989.
4. Z. Yanfu, Y. Suge. Single Event Soft Error in Advanced Integrated Circuit // Journal of Semi¬conductors. Vol. 36. № 11, P. 1–14. 2015.
5. Calin T., Nicolaidis M., and Velazco R. Upset Hardened Memory Design for Submicron CMOS Technology // Nuclear Science, IEEE Transactions on — 1996, Vol. 43, Issue 6, Part 1, pp. 2874–2878.
6. Whitaker S., Canaris J., and Liu K. SEU Hardened Memory Cells for a CCSDS Reed-Solomon Encoder // Nuclear Science, IEEE Transactions on — 1991, Vol. 38, Issue 6, Part 1, pp. 1471–1477.
7. Velazco R., Bessot D., Duzellier S., Ecoffet R., and Koga R. Two CMOS Memory Cells Suitable for the Design of SEU-tolerant VLSI Circuits // Nuclear Science, IEEE Transactions on — 1994, Vol. 41, Issue 6, Part 1–2, pp. 2229–2234.
8. Riadul Islam. A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-flop // Quality Electronic Design (ISQED), 2012 13th International Symposium on, 2012, pp. 347–352.
9. Timoshenkov V. P., Fateev I. A. DICE KMOP KNI-trigger, ustoichivyi k vozdei¬stviyu tyazhelykh zaryazhennykh chastits dlya primeneniya v priemnykh traktakh // Izv. vuzov. Elektronika. — 2017. Vol. 22. № 4. P. 402–406. DOI: 10.214151/1561-5405-2017-22-4-402-406. (In Russian).
10. Polovko A. M., Gurov S. V. Osnovy teorii nadezhnosti, Izd. 2-e, BKhV-Peterburg, 2006.702 p. (In Russian).
11. Bakit'ko R. V., Boldenkov E. N., Bu-¬lav¬skii N. T., i pr. GLONASS. Prin¬tsi¬py postroeniya i funktsioni¬rovaniya. Izd. 4-e, M.: Radiotekhnika, 2010. 800 p. (In Russian).
Space vehicles during their active service life in cosmic space are exposed to the impact of various factors. Fluxes of high energy elementary particles are one of the main factors affecting reliable functioning of microcircuits, constituting a part of air-borne equipment.
The impact of heavy charged particles on VLSIs results in various upsets of their operation and even may lead to catastrophic failures. In the course of the particle passage through semiconductor’s material a heavy charged particle track is left with the footprint located on semiconductor’s surface; the larger is the footprint diameter, the higher is the particle energy [1–3]. The activated electron-hole pairs with charge Q initiate current and voltage impulse at one of the contacts. The margin of upset resistance is characterized by Qcrit or critical charge required for triggering the storage element and for causing upset. If collected charge caused by heavy charged particle impact is less than critical one (Q < Qcrit), temporary signal level disturbance occurs at storage elements output without their subsequent state change.
An increase in performance is attributed to a decrease in minimum feature size, which in its turn results in the reductions of voltage supply, internal capacities, critical charge and an increase in vulnerability to single nuclear particles impact. At the same time, the effect of total accumulated doze decreases with reduction of oxides thickness. That is why predominance of single events effect (SEE) over ionization doze (TID) is typical for modern CMOS microcircuits [4].
SINGLE EVENTS MITIGATION
Currently there is a large number of investigations devoted to developing new variants of upset resistant cells, such as DICE, NASA, HIT, Hiper [6–9]. Increase in upset resistance in these cells is attained by additional data copies and internal feedbacks used for state restoring. With application of special-purpose cells, vulnerability to SEU of CMOS circuit reduces. In this case single event transient (SET) contribution in upset rate increases.
Single event transient appears in the form of short voltage pulse at combination logic input under heavy charged particle impact. With further propagation through the circuit this pulse may be written into memory cell distorting stored data. Circuit susceptibility to SET strongly depends on the operating frequency and size of “vulnerability window”, time segment near active share plane of clock signal [8].
Special attention should be paid to clock tree elements. In case of SET appearance at clock input, anomalous data may be written inside triggers. This research analyses how the clock gating cell affects memory registers upset resistance. Clock gating cells implementation is a part of standard design route and may be performed automatically, using special options of logical synthesis software (Fig. 1). The principle of clock gating cell operation consists in the following: in the presence of enabling signal at the input (EN = “1”) the clock signal passes through the cell at triggers register, in the presence of disabling signal the clock signal is interlocked.
PROBABILITY OF FAULTLESS OPERATION WITH CLOCK GATING CELL AND WITHOUT IT
As the probability of faultless system operation is equal to the product of faultless operation probabilities of its parts [10], it is possible to compute probability of faultless circuit operation Pwocg without clock gating cell as presented on Fig. 2:
where QD is probability of single event at trigger, QEN — probability of single event on EN node, QMUX — probability of single event at multiplexer, QBUF — probability of single event at clock tree buffer, QCLK — probability of single event at clock tree, N — register word length, К — amount of clock buffers.
Probability of faultless circuit operation with clock gating cell presented on Fig. 3 can be computed similarly:
where QD is probability of single event at trigger, QEN — probability of single event on EN node, QBUF — probability of single event at clock tree buffer, QCLK — probability of single event at clock tree, QCG — probability of single event at clock tree, N — register word length, К — amount of clock buffers.
Let us assume the following:
• Probabilities of single events for all triggers are identical;
• Window of vulnerability (WoV) is the same.
These assumptions may be done proceeding from the fact that while designing complex digital systems libraries of standard cell are applied. Therefore, triggers will have identical layout and, correspondingly, identical characteristics in terms of critical charge and internal nodes capacities.
Consequently, it is possible to express the ratio of faultless operation probabilities with clock gating cell and without it by the following formula:
.(1)
From (1) one can see that the ratio of faultless operation probabilities for circuits with clock gating cell and without it reduces to a probability of SET arising at multiplexor or at clock gating cell.
METHODS OF CALCULATING SET ARISING PROBABILITY
First, it is necessary to examine the probability of SET arising for NAND-cell presented on Fig. 4.
Probability of SET arising at NAND-cell input may be divided into two constituents. SET may arise as a result of impact on internal transistors QINT or as a result of external impacts on input nodes QEXT.
Probability of SET arising for internal transistors depends on actual condition of input signals. For combinations at AB input equalling “00”, output equals “1”; then in case of heavy charged particle impact on reversely biased p-n junction of 2nd transistor, transient process from “1” to “0” may arise. In a similar way it is possible to determine probability for each combination of input data. Assuming the duty ratio of input signals being equal to ¼ in any possible state, we can compute:
(2)
where Q0, Q1, Q2, Q3 are probabilities of SET arising at transistors presented on Fig. 4.
Probability of SET arising at external inputs also depends on the state and can be computed by the following formula:
(3)
where QAR, QBR are probabilities of negative SET arising, QBF, QAF — probabilities of positive SET arising at inputs, resulting in change of output voltage.
Let us introduce two new indices, QNANDR and QNANDF. QNANDR are probabilities of negative SET arising in case of output value “1”. QNANDF is probability of positive SET arising in case of output value “0”. These indices can be calculated using formulas (4) and (5):
(4)
(5)
where QINTF and QINTR are probabilities of positive and negative pulse of transient process, caused by heavy charged particle impact on “closed” transistors of NAND cell.
This method can be used for estimating probability of SET arising in inverter cell presented on Fig. 5.
Probability of SET arising at inverter input may be estimated using formulas (6) and (7):
(6)
where QAF is probability of positive SET arising at inverter input А and Q4 — probability of SET arising in “closed” 4th transistor.
(7)
where QAR is probability of negative SET arising at inverter input А and Q5 — probability of SET arising in “closed” 5th transistor.
ESTIMATING PROBABILITY OF SET ARISING AT CLOCK GATING CELL AND AT MULTIPLEXOR
Let us take a look at the structure of presented on Fig. 6 multiplexor.
Using formulas (4)–(7) it is possible to calculate probabilities of SET arising for all internal nodes. So, for N node we obtain:
(8)
(9)
where QKR, QKF, QLR, QLF — are probabilities of SET arising for nodes K and L respectively.
Adding the results of (8) and (9) we will obtain probability of SET arising for node N, that is QMUX.
Let us examine the next structure of clock gating cell presented on Fig. 7.
Taking in consideration that “latch” consists of two cells of inverter, it is possible to estimate the probability of positive and negative SET arising for P node:
(10)
(11)
where QENF and QENR are probabilities of negative and positive voltage pulse arising at EN input, t — “window of vulnerability” (WoV) size, T — clock cycle.
Using expressions (12) and (13) we can calculate the probability of SET arising for R node, that is QMUX.
(12)
(13)
Fig. 8 presents a diagram of QN and QR depending on SET arising probability at internal nodes. On this figure one can see that QN surpasses QR.
Fig. 9 presents a diagram of Pcg/Pwocg ratio depending on probability of SET arising at internal nodes in logarithmic scale for 32 and 8 triggers in register. On this diagram one can see that probability of circuit faultless operation with clock gating cell is higher than without it. Besides, with an increase in register capacity, the advantage of variant with clock gating cell is growing.
Let us calculate in a similar way faultless circuit operation probabilities with and without clock gating cell for standard “latches”, for latches of DICE-type, variants with sparse signal EN. It should be noted that in case of sparse EN the following assumption was made: EN very seldom transits from “0” into “1”, which means that QENF tends to 0. This variant of operation is typical for configuration registers in reception paths, in which data variations occur once in several millions of clocks [11].
Fig. 10 presents a diagram of faultless circuit operation probability with clock gating cell and standard “latch” (STD and STDLR — sparse signal EN), with clock gating cell and DICE “latch” (DICE and DICELR) and without clock gating cell (MUX and MUXLR).
RESULTS
The research has resulted in a method making it possible to conduct qualitative comparison of combinational circuits. It has been found that the application of clock gating cells enables one to increase faultless operation probability for registers of arbitrary word length, while an increase in word length leads to an increase in relative probability of faultless operation for circuits with clock gating cell. The calculations have shown that to increase faultless operation probability clock gating cells have to be automatically installed on registers whose capacity is no less than 1, instead of capacity 3 in accordance with low power ideology. The application of a “latch” of DICE type in clock gating cell will make it possible not only to reduce the probability of SEU arising in the cell, but also to reduce the probability of SEU arising in the whole circuit.
REFERENCES
1. Chumakov A. I. Deistvie kosmicheskoi radiatsii na integral'nye skhemy. M.: Radio i svyaz', 2004. 320 p. (In Russian).
2. Tapero K. I., Ulimov V. N., Chlenov A. M. Radiatsionnye effekty v kremnievykh integral'nykh skhemakh kosmicheskogo primeneniya. M.: BINOM. Laboratoriya znanii, 2012. 304 p. (In Russian).
3. Ionizing Radiation Effects in MOS Devices and Circuits / Ed. by T.-P. Ma and P. V. Dressendorfer. — N.-Y.: Wiley, 1989.
4. Z. Yanfu, Y. Suge. Single Event Soft Error in Advanced Integrated Circuit // Journal of Semi¬conductors. Vol. 36. № 11, P. 1–14. 2015.
5. Calin T., Nicolaidis M., and Velazco R. Upset Hardened Memory Design for Submicron CMOS Technology // Nuclear Science, IEEE Transactions on — 1996, Vol. 43, Issue 6, Part 1, pp. 2874–2878.
6. Whitaker S., Canaris J., and Liu K. SEU Hardened Memory Cells for a CCSDS Reed-Solomon Encoder // Nuclear Science, IEEE Transactions on — 1991, Vol. 38, Issue 6, Part 1, pp. 1471–1477.
7. Velazco R., Bessot D., Duzellier S., Ecoffet R., and Koga R. Two CMOS Memory Cells Suitable for the Design of SEU-tolerant VLSI Circuits // Nuclear Science, IEEE Transactions on — 1994, Vol. 41, Issue 6, Part 1–2, pp. 2229–2234.
8. Riadul Islam. A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-flop // Quality Electronic Design (ISQED), 2012 13th International Symposium on, 2012, pp. 347–352.
9. Timoshenkov V. P., Fateev I. A. DICE KMOP KNI-trigger, ustoichivyi k vozdei¬stviyu tyazhelykh zaryazhennykh chastits dlya primeneniya v priemnykh traktakh // Izv. vuzov. Elektronika. — 2017. Vol. 22. № 4. P. 402–406. DOI: 10.214151/1561-5405-2017-22-4-402-406. (In Russian).
10. Polovko A. M., Gurov S. V. Osnovy teorii nadezhnosti, Izd. 2-e, BKhV-Peterburg, 2006.702 p. (In Russian).
11. Bakit'ko R. V., Boldenkov E. N., Bu-¬lav¬skii N. T., i pr. GLONASS. Prin¬tsi¬py postroeniya i funktsioni¬rovaniya. Izd. 4-e, M.: Radiotekhnika, 2010. 800 p. (In Russian).
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