rus
Issue #7-8/2018
А.Afanasiev, V.Iljin, V.Luchinin, А.Mikhailov
Vapour Phase Epitaxy as the Key Technology for Power MIS -transistors Based on Silicon Carbide
Vapour Phase Epitaxy as the Key Technology for Power MIS -transistors Based on Silicon Carbide
Paper reports on features of SiC epitaxial growth in 4H–SiC vertical power MOSFET fabrication technology: for the drift layer formation and electrical properties optimization of the transistor channel. SiC components of power electronics have several advantages in comparison with traditional silicon ones. These components are characterized by higher electrical breakdown voltage, low active area resistance, high operating frequency, low losses at switching, high values of peak operating temperature and switching power density. Technologies of volume and epitaxial growth are the elements which enabled to create an electronic component basis for the 4H–SiC-based power electronics. Improvement of the epitaxial growth technology and quality of substrates permit to prepare instrument structures that demonstrate an advantage of SiC as the material of power electronics compared to other semiconductors.
Теги: buried channel drift layer epitaxy mosfet power electronics silicon carbide заглубление канала карбид кремния мдп-транзистор силовая электроника эпитаксия
INTRODUCTION
The demand for power electronics is determined by the main trends in the modern society development, one of them being an increase in the energy consumption volume. According to the international energy agencies data [1, 2], consumption of the electrical energy in the world for the last 25 years has doubled and continues to grow. Obviously, the higher efficiency of the electrical energy use will reduce consumption of non- renewable natural resources and diminish anthropogenic impact on the biosphere. One of the ways to raise efficiency of the energy supply systems is to reduce electrical losses when converting and switching of electricity.
Nowadays, power electronics devices are mainly manufactured using the most accessible and technologically familiar semiconductor – silicon. Use of polytype silicon carbide 4H (4H–SiC) as the base material for power electronics allows us to significantly enhance efficiency of the power systems. Unique electrophysical properties of 4H–SiC (Fig.1) determine a possibility of creating a new generation power, pulsed, high-temperature and radiation-resistant ECB on its basis [3–6]. A higher avalanche breakdown field strength in 4H-SiC compared to silicon [7–9] allows of increasing of the doping level of the power device drift region and to decrease its thickness, and, therefore, significantly lower resistance compared to the silicon analog and, as a result, resistive (static) losses in it. Low resistance of the active region allows of using high-frequency unipolar devices based on 4H–SiC instead of the existing bipolar devices on silicon. This permits us to increase an operating frequency of power devices and use smaller passive components. Low static and dynamic losses in the 4H–SiC-based devices (also due to a low concentration of the minority charge carriers), together with high thermal conductivity and maximum operating temperature, make it possible to operate them without forced cooling. The above factors determine superiority of silicon carbide power electronics over silicon and allow to reduce mass, volume, electrical losses and cost of the entire power system (Fig.2) [10].
Current level of the 4H–SiC MIS-transistors development can be estimated in Fig.3 where parameters of 4H–SiC and Si-based MIS-transistor produced by various manufacturers and theoretical limits of the unipolar devices are presented. It can be seen that the manufacturing technology of silicon-based MIS-transistors has exhausted itself and, thanks to a number of technical and technological solutions [11], even surpassed its theoretical limit, while the technology of 4H–SiC based MIS-transistors requires further development, despite a significant progress made in recent decades.
In this paper we present results of the developments achieved in St. Petersburg Electrotechnical University "LETI" in the field of creating MIS-transistors based on 4H–SiC. This work is aimed at studying a possibility of improving the technical and operational parameters of transistors manufactured using the ion implantation and vapour phase epitaxy technology, as compared with those previously developed in [3, 5, 12].
For a long time the development of SiC electronics was hindered by absence of a technology for growing high-quality large-size SiC crystals. Development of a new method for growing bulk SiC crystals at the Leningrad Electrotechnical Institute (1978) by Yu.M.Tairov and V.F.Tsvetkov on the basis of a modification of the Lely method (the LETI method) [13] made it possible to obtain large-size SiC substrates and marked the beginning of the stage of industrial development of SiC technology [14]. It is difficult to overestimate importance of this development and its impact on the future of all power electronics.
The chemical vapour deposition (CVD) is the main method for growing high-quality 4H–SiC epitaxial structures from the gas phase. The advantage of CVD technology is that, in the gaseous state, the Si/C ratio can be controlled during growth of epitaxial layers.
The most important task in SiC-CVD epitaxy is to ensure high quality of epitaxial layers in terms of polytype replication (stable reproducibility of the polytype of the substrate by epitaxial layer), morphology, doping level and thickness. These indicators are associated with the technological parameters of the process, which must be controlled (Fig.4). Epitaxy of 4H–SiC is carried out at high temperatures (1 550... 1 750 °C) on substrates artificially deviated from the base crystallographic planes [15], which makes it possible to inherit the crystal structure of the substrate and avoid the inclusion of other polytypes in the grown epitaxial layer. During epitaxy, the SiC layers are doped by introducing doping impurities into the reaction chamber (Al to form a p-type conductivity layer and N to form an n-type layer) in a wide concentration range: 1 · 1014… 2 · 1019 cm–3 – for N and 5 · 1014... 5 · 1020 cm–3 – for Al. Since the mobility of electrons in 4H–SiC is significantly higher than the mobility of holes, in practice they create MIS-transistors with an n-channel, which is induced in the p-region formed by ion implantation.
To this end, a high-alloyed n-type substrate of a given thickness is formed by the epitaxial layer with a certain nitrogen concentration in accordance with the calculated breakdown voltage. At the same time, in order to reduce the number of defects inherited from the substrate to the epitaxial layer, a thin buffer n+-layer is formed first [16].
Thickness of the drift region Wd and concentration of the dopant Nd in it are calculated based on the breakdown voltage Vb of the designed MIS-transistor and the field strength of the avalanche breakdown of the Ecrit semiconductor, which depends on the dopant concentration [17, 18]. There exist two approaches to calculating these parameters: the NPT-approach and the PT-approach.
According to the NPT-approach, Wd and Nd are chosen so that at breakdown of the structure the field distribution has a triangular shape, the maximum field strength in the metallurgical p–n-junction boundary being equal to the semiconductor avalanche breakdown field (Fig.5).
The triangle area is equal to the voltage applied to the MOS-transistor. At high breakdown voltages, the contact potential difference is negligible, and in case of an abrupt asymmetrical p-n-junction, calculations are performed in accordance with the following expressions [9, 17, 18] (Fig.6, a):
form01_eng.ai (1)
and
form02_eng.ai (2)
The reduced resistance of the drift area can be found from the equation (Fig.6, b):
form03_eng.ai, (3)
where μn = μn(Nd) – a mobility of electrons in a drift area.
Minimization of the reduced resistance of a transistor is an important task, because low resistance decreases the static losses in the device or reduces its area, which leads to cost reduction and often gives a decisive competitive advantage.
The PT-approach allows of reducing the drift area resistance at the same breakdown voltage (or of increasing the breakdown voltage at the same resistance). In this case, the parameters of the drift area are selected in such a way (see Fig.6, a) so that the field distribution has a trapezoidal shape (see Fig.5), and the field strength E1 in the p-n-junction "drift area – substrate" should be 1/3 from the field strength at the metallurgical boundary of the p-n-junction equal to Ecrit. This condition corresponds to the minimum of the function Rdrift sp(s), where s =E1/Ecrit [18]:
form04_eng.ai (4)
form05_eng.ai (5)
wherefrom
form06_eng.ai (6)
and
form07_eng_curv.ai(7)
Thus, at a given breakdown voltage, the minimum resistance of the drift area is achieved, which is ~ 15% lower than the resistance of the drift region designed in the framework of the NPT-approach (see Fig.6б).
The parameters of the drift region with a calculated breakdown voltage of 1,200 V:
Nd~1,5 ∙ 1016 sm–3, Wd ~ 9,2 μm,
Rdrift sp ~ 0,39 mΩ ∙ sm2 (NPT-approach);
Nd~1,3 ∙ 1016 sm–3, Wd ~ 7 μm,
Rdrift sp ~ 0,34 mΩ ∙ sm2 (PT-approach).
In practice, it is necessary to provide for some margin of the breakdown voltage due to presence of defects in the 4H–SiC crystal structure, possible deviations of thickness of the drift area and impurity concentration in it from the calculated values.
The drift area of the manufactured MIS-transistor was designed as part of the PT-approach for a breakdown voltage of ~ 2000 V with Rdrift sp ~ 1.1 mΩ ∙ cm2 (Nd ~ 7 ∙ 1015 cm–3, Wd ~ 13 μm). The drift region, designed for the same voltage within the NPT-approach, would be Rdrift sp ~ 1.3 mΩ ∙ cm2. In addition to the formation of the drift area, epitaxial growth technology of 4H–SiC can be used to bury the transistor channel. According to the simulation results, two epitaxial layers were formed in the "Medici TCAD" software package: an n-type lower layer 50 nm thick with a doping level of 1 ∙ 1017 cm–3 and a p-type upper layer 50 nm thick with a doping level of 2 ∙ 1016 cm–3.
The structure of the active area of the power MIS-transistor with a buried channel is shown in Fig.7. The insets show the concentration profiles of the dopant in the corresponding cross sections of the structure. In accordance with the simulation results, an n-type epitaxial layer in the channel area must be completely depleted due to the upper p-type epitaxial layer and the high-alloyed p-region, and such a MIS-transistor must be locked at zero gate voltage.
Formation of the buried channel by growing epitaxial layers on a high-doped p-region allows us to significantly increase mobility of the charge carriers in the transistor channel by reducing the Coulomb scattering of free charge carriers on charged traps, since the electron current flows further from the 4H–SiC/SiO2. The higher mobility of the charge carriers is also due to the fact that the SiC layer doped during epitaxy has no defects resulting from the bombardment of the SiC surface with high-energy Al ions during formation of the high-alloyed p-region by ion implantation.
The power vertical MIS-transistors with a buried channel (BC) and without (N2O) were formed from an array of hexagonal cells and floating guard rings located around the device perimeter, in accordance with the previously developed topology [12]. The transistor cell had a width of 13 μm at a channel length of 1 μm and a JFET width of 3 μm. Images of one of the manufactured power MIS-transistors are shown in Fig.8. The gate dielectric was formed by thermal oxidation in N2O. atmosphere.
The manufactured transistor chips, consisting of ~ 37,000 cells and having an active area of ~ 5.4 mm2, were installed into a КТ-105-1 case with subsequent unwinding of the leads.
Output characteristics of the enclosed devices are shown in Fig.9. The reduced resistance of Rds(on) sp transistors equaled 23.8 and 7.3 mΩ ∙ cm2 for N2O and BC transistors, respectively. The BC transistor is capable of switching a current up to 83 A in a pulsed mode (with Vgs = 20 V and Vds = 20 V), which corresponds to a current density of about 1,500 A / cm2 and is associated with its low resistance in the "switched on" state.
CONCLUSIONS
Thus, vapour phase epitaxy of silicon carbide processes make an integral component of the technological route when manufacturing power MIS-transistors on 4H–SiC at a stage of creating the basic epitaxial n-n+ structure that provides for the required breakdown voltage and optimum resistance of the drift region. The channel burying technology, implemented by the CVD-growth method of 4H–SiC epitaxial layers in the p+ region, can significantly reduce resistance of the transistor in the "switched on" state. ■
The research was made with the financial support of The Ministry of Education and Science of the Russian Federation (project No. 03.G25.31.0243).
The demand for power electronics is determined by the main trends in the modern society development, one of them being an increase in the energy consumption volume. According to the international energy agencies data [1, 2], consumption of the electrical energy in the world for the last 25 years has doubled and continues to grow. Obviously, the higher efficiency of the electrical energy use will reduce consumption of non- renewable natural resources and diminish anthropogenic impact on the biosphere. One of the ways to raise efficiency of the energy supply systems is to reduce electrical losses when converting and switching of electricity.
Nowadays, power electronics devices are mainly manufactured using the most accessible and technologically familiar semiconductor – silicon. Use of polytype silicon carbide 4H (4H–SiC) as the base material for power electronics allows us to significantly enhance efficiency of the power systems. Unique electrophysical properties of 4H–SiC (Fig.1) determine a possibility of creating a new generation power, pulsed, high-temperature and radiation-resistant ECB on its basis [3–6]. A higher avalanche breakdown field strength in 4H-SiC compared to silicon [7–9] allows of increasing of the doping level of the power device drift region and to decrease its thickness, and, therefore, significantly lower resistance compared to the silicon analog and, as a result, resistive (static) losses in it. Low resistance of the active region allows of using high-frequency unipolar devices based on 4H–SiC instead of the existing bipolar devices on silicon. This permits us to increase an operating frequency of power devices and use smaller passive components. Low static and dynamic losses in the 4H–SiC-based devices (also due to a low concentration of the minority charge carriers), together with high thermal conductivity and maximum operating temperature, make it possible to operate them without forced cooling. The above factors determine superiority of silicon carbide power electronics over silicon and allow to reduce mass, volume, electrical losses and cost of the entire power system (Fig.2) [10].
Current level of the 4H–SiC MIS-transistors development can be estimated in Fig.3 where parameters of 4H–SiC and Si-based MIS-transistor produced by various manufacturers and theoretical limits of the unipolar devices are presented. It can be seen that the manufacturing technology of silicon-based MIS-transistors has exhausted itself and, thanks to a number of technical and technological solutions [11], even surpassed its theoretical limit, while the technology of 4H–SiC based MIS-transistors requires further development, despite a significant progress made in recent decades.
In this paper we present results of the developments achieved in St. Petersburg Electrotechnical University "LETI" in the field of creating MIS-transistors based on 4H–SiC. This work is aimed at studying a possibility of improving the technical and operational parameters of transistors manufactured using the ion implantation and vapour phase epitaxy technology, as compared with those previously developed in [3, 5, 12].
For a long time the development of SiC electronics was hindered by absence of a technology for growing high-quality large-size SiC crystals. Development of a new method for growing bulk SiC crystals at the Leningrad Electrotechnical Institute (1978) by Yu.M.Tairov and V.F.Tsvetkov on the basis of a modification of the Lely method (the LETI method) [13] made it possible to obtain large-size SiC substrates and marked the beginning of the stage of industrial development of SiC technology [14]. It is difficult to overestimate importance of this development and its impact on the future of all power electronics.
The chemical vapour deposition (CVD) is the main method for growing high-quality 4H–SiC epitaxial structures from the gas phase. The advantage of CVD technology is that, in the gaseous state, the Si/C ratio can be controlled during growth of epitaxial layers.
The most important task in SiC-CVD epitaxy is to ensure high quality of epitaxial layers in terms of polytype replication (stable reproducibility of the polytype of the substrate by epitaxial layer), morphology, doping level and thickness. These indicators are associated with the technological parameters of the process, which must be controlled (Fig.4). Epitaxy of 4H–SiC is carried out at high temperatures (1 550... 1 750 °C) on substrates artificially deviated from the base crystallographic planes [15], which makes it possible to inherit the crystal structure of the substrate and avoid the inclusion of other polytypes in the grown epitaxial layer. During epitaxy, the SiC layers are doped by introducing doping impurities into the reaction chamber (Al to form a p-type conductivity layer and N to form an n-type layer) in a wide concentration range: 1 · 1014… 2 · 1019 cm–3 – for N and 5 · 1014... 5 · 1020 cm–3 – for Al. Since the mobility of electrons in 4H–SiC is significantly higher than the mobility of holes, in practice they create MIS-transistors with an n-channel, which is induced in the p-region formed by ion implantation.
To this end, a high-alloyed n-type substrate of a given thickness is formed by the epitaxial layer with a certain nitrogen concentration in accordance with the calculated breakdown voltage. At the same time, in order to reduce the number of defects inherited from the substrate to the epitaxial layer, a thin buffer n+-layer is formed first [16].
Thickness of the drift region Wd and concentration of the dopant Nd in it are calculated based on the breakdown voltage Vb of the designed MIS-transistor and the field strength of the avalanche breakdown of the Ecrit semiconductor, which depends on the dopant concentration [17, 18]. There exist two approaches to calculating these parameters: the NPT-approach and the PT-approach.
According to the NPT-approach, Wd and Nd are chosen so that at breakdown of the structure the field distribution has a triangular shape, the maximum field strength in the metallurgical p–n-junction boundary being equal to the semiconductor avalanche breakdown field (Fig.5).
The triangle area is equal to the voltage applied to the MOS-transistor. At high breakdown voltages, the contact potential difference is negligible, and in case of an abrupt asymmetrical p-n-junction, calculations are performed in accordance with the following expressions [9, 17, 18] (Fig.6, a):
form01_eng.ai (1)
and
form02_eng.ai (2)
The reduced resistance of the drift area can be found from the equation (Fig.6, b):
form03_eng.ai, (3)
where μn = μn(Nd) – a mobility of electrons in a drift area.
Minimization of the reduced resistance of a transistor is an important task, because low resistance decreases the static losses in the device or reduces its area, which leads to cost reduction and often gives a decisive competitive advantage.
The PT-approach allows of reducing the drift area resistance at the same breakdown voltage (or of increasing the breakdown voltage at the same resistance). In this case, the parameters of the drift area are selected in such a way (see Fig.6, a) so that the field distribution has a trapezoidal shape (see Fig.5), and the field strength E1 in the p-n-junction "drift area – substrate" should be 1/3 from the field strength at the metallurgical boundary of the p-n-junction equal to Ecrit. This condition corresponds to the minimum of the function Rdrift sp(s), where s =E1/Ecrit [18]:
form04_eng.ai (4)
form05_eng.ai (5)
wherefrom
form06_eng.ai (6)
and
form07_eng_curv.ai(7)
Thus, at a given breakdown voltage, the minimum resistance of the drift area is achieved, which is ~ 15% lower than the resistance of the drift region designed in the framework of the NPT-approach (see Fig.6б).
The parameters of the drift region with a calculated breakdown voltage of 1,200 V:
Nd~1,5 ∙ 1016 sm–3, Wd ~ 9,2 μm,
Rdrift sp ~ 0,39 mΩ ∙ sm2 (NPT-approach);
Nd~1,3 ∙ 1016 sm–3, Wd ~ 7 μm,
Rdrift sp ~ 0,34 mΩ ∙ sm2 (PT-approach).
In practice, it is necessary to provide for some margin of the breakdown voltage due to presence of defects in the 4H–SiC crystal structure, possible deviations of thickness of the drift area and impurity concentration in it from the calculated values.
The drift area of the manufactured MIS-transistor was designed as part of the PT-approach for a breakdown voltage of ~ 2000 V with Rdrift sp ~ 1.1 mΩ ∙ cm2 (Nd ~ 7 ∙ 1015 cm–3, Wd ~ 13 μm). The drift region, designed for the same voltage within the NPT-approach, would be Rdrift sp ~ 1.3 mΩ ∙ cm2. In addition to the formation of the drift area, epitaxial growth technology of 4H–SiC can be used to bury the transistor channel. According to the simulation results, two epitaxial layers were formed in the "Medici TCAD" software package: an n-type lower layer 50 nm thick with a doping level of 1 ∙ 1017 cm–3 and a p-type upper layer 50 nm thick with a doping level of 2 ∙ 1016 cm–3.
The structure of the active area of the power MIS-transistor with a buried channel is shown in Fig.7. The insets show the concentration profiles of the dopant in the corresponding cross sections of the structure. In accordance with the simulation results, an n-type epitaxial layer in the channel area must be completely depleted due to the upper p-type epitaxial layer and the high-alloyed p-region, and such a MIS-transistor must be locked at zero gate voltage.
Formation of the buried channel by growing epitaxial layers on a high-doped p-region allows us to significantly increase mobility of the charge carriers in the transistor channel by reducing the Coulomb scattering of free charge carriers on charged traps, since the electron current flows further from the 4H–SiC/SiO2. The higher mobility of the charge carriers is also due to the fact that the SiC layer doped during epitaxy has no defects resulting from the bombardment of the SiC surface with high-energy Al ions during formation of the high-alloyed p-region by ion implantation.
The power vertical MIS-transistors with a buried channel (BC) and without (N2O) were formed from an array of hexagonal cells and floating guard rings located around the device perimeter, in accordance with the previously developed topology [12]. The transistor cell had a width of 13 μm at a channel length of 1 μm and a JFET width of 3 μm. Images of one of the manufactured power MIS-transistors are shown in Fig.8. The gate dielectric was formed by thermal oxidation in N2O. atmosphere.
The manufactured transistor chips, consisting of ~ 37,000 cells and having an active area of ~ 5.4 mm2, were installed into a КТ-105-1 case with subsequent unwinding of the leads.
Output characteristics of the enclosed devices are shown in Fig.9. The reduced resistance of Rds(on) sp transistors equaled 23.8 and 7.3 mΩ ∙ cm2 for N2O and BC transistors, respectively. The BC transistor is capable of switching a current up to 83 A in a pulsed mode (with Vgs = 20 V and Vds = 20 V), which corresponds to a current density of about 1,500 A / cm2 and is associated with its low resistance in the "switched on" state.
CONCLUSIONS
Thus, vapour phase epitaxy of silicon carbide processes make an integral component of the technological route when manufacturing power MIS-transistors on 4H–SiC at a stage of creating the basic epitaxial n-n+ structure that provides for the required breakdown voltage and optimum resistance of the drift region. The channel burying technology, implemented by the CVD-growth method of 4H–SiC epitaxial layers in the p+ region, can significantly reduce resistance of the transistor in the "switched on" state. ■
The research was made with the financial support of The Ministry of Education and Science of the Russian Federation (project No. 03.G25.31.0243).
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